Fuse structure and method for manufacturing same
First Claim
1. A fuse structure comprising:
- a substrate;
a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface;
a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface; and
a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and comprising multiple barrier layers of different materials, wherein the entire surface of the planar barrier multilayer assembly facing away from the first chip surface is a planar surface that lies in a single plane and wherein portions of the planar surface are in direct mechanical contact with first and second areas of the metallization layer;
wherein the fuse conductive trace, the metallization layer, and the barrier multilayer assembly are disposed such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.
41 Citations
20 Claims
-
1. A fuse structure comprising:
-
a substrate; a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface; a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface; and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and comprising multiple barrier layers of different materials, wherein the entire surface of the planar barrier multilayer assembly facing away from the first chip surface is a planar surface that lies in a single plane and wherein portions of the planar surface are in direct mechanical contact with first and second areas of the metallization layer; wherein the fuse conductive trace, the metallization layer, and the barrier multilayer assembly are disposed such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18)
-
-
13. A method for manufacturing an electric device with a fuse structure, the method comprising:
-
depositing a first planar area and a second planar area of a metallization layer on a substrate so that the first planar area and the second planar area are separated from each other; forming a planar barrier multilayer assembly comprising multiple barrier layers of different materials, on the planar areas of the metallization layer, wherein the entire surface of the planar barrier multilayer assembly facing the metallization layer is a planar surface that lies in a single plane and wherein portions of the planar surface are in direct mechanical contact with the first and second planar areas of the metallization layer; and creating a fuse conductive trace on the barrier multilayer assembly so that cutting the fuse conductive trace and the barrier multilayer assembly would result in electrically isolating the first area of the metallization layer from the second area of the metallization layer. - View Dependent Claims (19, 20)
-
Specification