Accurate capacitance measurement for ultra large scale integrated circuits

• US 8,115,500 B2
• Filed: 01/27/2011
• Issued: 02/14/2012
• Est. Priority Date: 06/29/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Doong, Yih-Yuh, Chang, Keh-Jeng, Mii, Yuh-Jier, Liu, Sally, Hung, Lien Jung, Chang, Victor Chih Yuan
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US13/015,117
• Publication Number:
  US 20110168995A1
• Time in Patent Office: 383 Days
• Field of Search: None
• US Class Current: 324/687
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.

Claims

1. A test structure formed on a semiconductor substrate for measuring the parasitic capacitance between a via and adjacent conductive features of a semiconductive device, said test structure comprising:

said semiconductor substrate;

a first conductive element having a first regularly repeating pattern, formed in a first metal layer over the substrate;

a second conductive element having a second regularly repeating pattern, formed in the first metal layer over the substrate and electrically isolated from the first conductive element;

a third conductive element, having a third regularly repeating pattern, formed in a second metal layer over the substrate;

a fourth conductive element, having a fourth regularly repeating pattern, formed in the second metal layer and electrically isolated from the third conductive element, wherein said respective first, second, third, and fourth regularly repeating patterns comprise a comb structure;

a first pattern of regularly spaced vias electrically connecting the first and fourth conductive elements; and

a second pattern of regularly spaced vias electrically connecting the second and third conductive elements.

2. The test structure of claim 1, wherein the first pattern of regularly spaced vias are located at regions where fingers of the fourth conductive element overlay fingers of the first conductive element and the second pattern of regularly spaced vias are located at regions where fingers of the third conductive element overlay fingers of the second conductive element.

3. The test structure of claim 1, further comprising a first dielectric layer isolating the first and second conductive elements from the substrate and a second dielectric layer isolating the first and second conductive elements from the third and fourth conductive elements.

4. The test structure of claim 1, further comprising a first test probe pad coupled to the first and fourth conductive elements and a second test probe pad coupled to the second and third conductive elements.

5. The test structure of claim 1, wherein the first regularly repeating pattern corresponds to a minimum spacing design rule.

6. A test structure formed on a semiconductor substrate for measuring the parasitic capacitance between a via and adjacent conductive features of a semiconductive device, said test structure comprising:

a grid of equally spaced conductive elements,

a first plurality of the conductive elements being formed in a first plane, being substantially aligned in a first direction, and being electrically connected to one another;

a second plurality of the conductive elements being formed in the first plane, being substantially aligned in the first direction, being electrically connected to one another, and being electrically isolated from the first plurality of conductive elements;

a third plurality of the conductive elements being formed in a second plane, above the first plane, being substantially aligned in a second direction, and being electrically connected to one another;

a fourth plurality of the conductive elements being formed in the second plane, being substantially aligned in the first direction, and being electrically connected to one another, and being electrically isolated from the third plurality of conductive elements;

a first plurality of vias electrically connecting the first plurality of conductive elements with the fourth plurality of conductive elements at points where the fourth plurality of conductive elements overlaps the first plurality of conductive vias;

a second plurality of vias electrically connecting the second plurality of conductive elements with the third plurality of conductive elements at points where the third plurality of conductive elements overlaps the second plurality of conductive vias;

a first test probe pad connected to the first and fourth plurality of conductive elements; and

a second test probe pad connected to the second and third plurality of conductive elements.

7. The test structure of claim 6, wherein the first plurality of conductive elements form a comb structure and the second plurality of conductive elements form a complementary comb structure and wherein the third plurality of conductive elements form a comb structure and the fourth plurality of conductive elements form a complementary comb structure.

8. The test structure of claim 6, wherein the first plurality of vias and the second plurality of vias comprises 10,000 vias.

9. The test structure of claim 6, further comprising a common conductive element electrically connecting each of the first plurality of conductive elements and being aligned substantially orthogonally to the first plurality of conductive elements.

10. The test structure of claim 6, wherein the first direction is orthogonal to the second direction.

11. The test structure of claim 6, wherein the first plurality of vias and the second plurality of vias are formed in a dielectric layer.