Method for fabrication of a semiconductor device and structure

• US 8,115,511 B2
• Filed: 06/09/2010
• Issued: 02/14/2012
• Est. Priority Date: 04/14/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): Tran, Thienvu
• Application Number:
  US12/797,493
• Publication Number:
  US 20100259296A1
• Time in Patent Office: 615 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/39
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die.

Claims

1. A configurable integrated circuit (IC) system comprising:

a first die comprising input/output cells; and

a Field Programmable Gated Array (FPGA) second die substantially vertically connected by a first plurality of through-silicon-vias (TSVs) to the first die, wherein said FPGA second die comprises a plurality of unused predetermined dice lines, wherein said FPGA second die comprises at least two micro control units (MCUs), and at least one permanent connection to electrically interconnect said micro control units.

2. A configurable IC system according to claim 1, wherein said first die is fabricated by a process older than said FPGA second die.

3. A configurable IC system according to claim 1, further comprising:

a third die connected to at least one of said first die or said FPGA second die by a second plurality of through silicon-vias (TSVs).

4. A configurable IC system according to claim 1, wherein said first die further comprises serializer/deserializer (SerDes) circuits.

5. A configurable IC system according to claim 1, wherein said FPGA second die comprises:

a plurality of configurable logic cells, and

between one and two metal layers interconnecting said configurable logic cells across said unused predetermined dice lines.

13. The configurable IC system according to claim 1, wherein said plurality of unused predetermined dice lines allow FPGA dies of multiple die sizes to be constructed based on the same mask set.

6. A configurable IC system comprising:

a first die comprising input/output cells; and

a Field Programmable Gated Array (FPGA) second die connected by a first plurality of through-silicon-vias (TSV) to the first die;

wherein said FPGA second die comprises at least two micro control units (MCUs), and said FPGA second die further comprises at least one permanent connection to electrically interconnect said micro control units.

7. A configurable IC system according to claim 6, wherein said FPGA second die comprises a plurality of unused predetermined dice lines.

8. A configurable IC system according to claim 6, wherein said first die is fabricated in a process older than said FPGA second die.

9. A configurable IC system according to claim 6 wherein said FPGA second die further comprises a plurality of memory circuits.

10. A configurable IC system according to claim 6, wherein said first die further comprises serializer/deserializer (SerDes) circuits.

11. A configurable IC system according to claim 7, wherein said FPGA second die comprises a plurality of configurable logic cells and between one and two metal layers interconnecting said configurable logic cells across said unused predetermined dice lines.

12. The configurable IC system according to claim 6, wherein said permanent connection is made before said FPGA second die is connected to said first die by said first plurality of TSVs.