Method and system for matching networks embedded in an integrated circuit package

• US 8,115,567 B2
• Filed: 12/13/2007
• Issued: 02/14/2012
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza, Rofougaran, Maryam
• Primary Examiner(s): JONES, STEPHEN E
• Application Number:
  US11/956,071
• Publication Number:
  US 20090153261A1
• Time in Patent Office: 1,524 Days
• Field of Search: 333/33, 333/32, 333/246, 333/247
• US Class Current: 333/33
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H03H 7/38 : Impedance-matching networks

Abstract

Methods and systems for matching networks embedded in an integrated circuit package are disclosed and may include controlling impedance within an integrated circuit via one or more impedance matching networks. The impedance matching networks may be embedded within a multi-layer package bonded to the integrated circuit. The impedance of one or more devices within the integrated circuit may be configured utilizing the impedance matching networks. The multi-layer package may include one or more impedance matching networks. The impedance matching networks may provide impedance matching between devices internal to the integrated circuit and external devices. The impedance matching networks may be embedded within the multi-layer package, and may include transmission lines, inductors, capacitors, transformers and/or surface mount devices. The impedance matching networks may be deposited on top of and/or on bottom of the multi-layer package. The integrated circuit may be flip-chip bonded to the multi-layer package.

Claims

1. A multi-layer package that is flip-chip bonded to an integrated circuit, the multi-layer package comprising:

an impedance matching network comprising a ferromagnetic material device; and

one or more microelectromechanical system switches operable to dynamically configure the impedance matching network.

2. The multi-layer package according to claim 1, wherein the impedance matching network comprises a transmission line.

3. The multi-layer package according to claim 1, wherein the impedance matching network comprises an inductor.

4. The multi-layer package according to claim 1, wherein the impedance matching network comprises a capacitor.

5. The multi-layer package according to claim 1, wherein the impedance matching network comprises a transformer.

6. The multi-layer package according to claim 1, wherein the impedance matching network comprises a surface mount device.

7. A system for enabling communication, the system comprising:

a multi-layer package that is flip-chip bonded to an integrated circuit, wherein said multi-layer package comprises one or more impedance matching networks, said one or more impedance matching networks comprise ferromagnetic material devices, and wherein said impedance matching networks are dynamically configured utilizing MEMS switches.

8. The system according to claim 7, wherein devices internal to said integrated circuit are impedance matched to external devices utilizing said impedance matching networks.

9. The system according to claim 7, wherein said impedance matching networks are embedded within said multi-layer package.

10. The system according to claim 7, wherein said impedance matching networks comprise transmission lines.

11. The system according to claim 7, wherein said impedance matching networks comprise inductors.

12. The system according to claim 7, wherein said impedance matching networks comprise capacitors.

13. The system according to claim 7, wherein said impedance matching networks comprise transformers.

14. The system according to claim 7, wherein said impedance matching networks comprise surface mount devices.

15. A method for enabling communication, the method comprising:

controlling impedance within an integrated circuit via one or more impedance matching networks, wherein said one or more impedance matching networks are integrated in and/or on a multi-layer package flip-chip bonded to said integrated circuit, said one or more impedance matching networks comprise ferromagnetic material devices, and wherein said impedance matching networks are dynamically configured utilizing MEMS switches.

16. The method according to claim 15, comprising configuring the impedance of one or more devices within said integrated circuit utilizing said impedance matching networks.

17. The method according to claim 15, wherein said impedance matching networks are embedded within said multi-layer package.

18. The method according to claim 15, wherein said impedance matching networks comprise transmission lines.

19. The method according to claim 15, wherein said impedance matching networks comprise inductors.

20. The method according to claim 15, wherein said impedance matching networks comprise capacitors.

21. The method according to claim 15, wherein said impedance matching networks comprise transformers.

22. The method according to claim 15, wherein said impedance matching networks comprise surface mount devices.