Active inductor for ASIC application

• US 8,115,575 B2
• Filed: 08/14/2008
• Issued: 02/14/2012
• Est. Priority Date: 08/14/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis Lu-Chen, Guo, Jong-Ru, Wang, Ping-Chuan, Yang, Zhijian
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US12/191,519
• Publication Number:
  US 20100039191A1
• Time in Patent Office: 1,279 Days
• Field of Search: 333/213, 333/214, 333/215, 333/216, 333/217
• US Class Current: 333/214
• CPC Class Codes: H03H 11/08 using gyrators
• CPC Class Codes: H03H 11/48 simulating reactances

Abstract

An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

Claims

1. An active inductor comprising first and second nMOS devices, said first and second nMOS devices respectively having a source, a drain and a gate, first and second capacitors, and a resistor;

wherein the gate of the first nMOS device is attached to the drain of the second nMOS device, the drain of the first nMOS device is coupled to the drain of the second nMOS device through the first capacitor and the resistor, and the source of the first nMOS device is coupled to the source of the second nMOS device through the second capacitor.

2. The active inductor as recited in claim 1 wherein the drain of the first nMOS device coupled to the drain of the second nMOS device through the first capacitor connected in series to the resistor form a feedback path.

3. The active inductor as recited in claim 1 further comprising positive and negative ports formed, respectively, by the gate and source of the second nMOS device.

4. The active inductor as recited in claim 1 wherein the first and second capacitors respectively have a capacitance ranging from 100 fF to 1 pF, and the resistor has a resistance ranging from 50 ohms to 1000 ohms.

5. The active inductor as recited in claim 1, wherein said first and second nMOS devices, first and second capacitors and said resistors are formed by CMOS, DRAM, or SRAM process integration techniques.

6. The active inductor as recited in claim 1, wherein said first and second capacitors are deep-trench capacitors.

7. The active inductor as recited in claim 1, wherein said first and second capacitors are stack capacitors.

8. The active inductor as recited in claim 1, wherein said first and second capacitors are MOS capacitors.

9. The active inductor as recited in claim 1, wherein said first and second capacitors are electrically isolated from one another.

10. The active inductor as recited in claim 1, wherein said first and second capacitors are respectively formed in a first isolated well and in a second isolated well.

11. The active inductor as recited in claim 1, wherein said resistor is a polysilicon resistor.

12. The active inductor as recited in claim 1, wherein said resistor is a back-end-of-line silicide resistor or a TaN resistor.

13. A parallel arrangement of a plurality of active inductors to form an inductor configuration having a reduced inductance wherein positive ports of the plurality of active inductors are connected to a common positive port, and negative ports of the plurality of active inductors are connected to a common negative port, each of said active inductors comprising a first and second nMOS devices respectively having a source, drain and gate, first and second capacitors, and a resistor, the gate of the first nMOS device is connected to the drain of the second nMOS device, the drains of the first and second nMOS are coupled to each others through the first capacitor in series with the resistor, and the source of the first nMOS device is coupled to the source of the second nMOS device through the second capacitor, and wherein the common positive port and the common negative port are, respectively, the positive port and the negative port of the plurality of the active inductors form the inductor configuration.