RFID tags with synchronous power rectifier

• US 8,115,597 B1
• Filed: 03/04/2008
• Issued: 02/14/2012
• Est. Priority Date: 03/07/2007
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Hyde, John D., Peach, Charles J. T.
• Primary Examiner(s): Bugg, George
• Assistant Examiner(s): OBINIYI, PAUL I
• Application Number:
  US12/042,117
• Time in Patent Office: 1,442 Days
• Field of Search: 340 101- 106, 3405721-5729, 235/380, 235/235, 235375-385
• US Class Current: 340/10.1
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: H04Q 2213/1308 Power supply
• CPC Class Codes: H04Q 2213/13095 PIN / Access code, authentication

Abstract

The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating region. During the same time additional control signals are applied to the gates of the transistors, the control signals are synchronous, but out of phase, with each other.

Claims

1. A power rectifier for a Radio Frequency Identification tag circuit, comprising:

a first antenna input node for receiving a first phase of an alternating RF wireless signal;

a second antenna input node for receiving a second phase of the alternating RF wireless signal which is substantially opposite to the first phase;

a plurality of serially coupled stages, at least one of the stages including

a first synchronous element with a first beginning coupled to receive the second phase and a first ending, the first synchronous element including;

a first transistor having an input terminal at the first beginning, an output terminal, and a gate coupled to receive the first phase; and

a second transistor having an input terminal, an output terminal at the first ending, and a gate coupled to receive the second phase, in which the input terminal of the second transistor is connected to the output terminal of the first transistor at a first intermediate node so as to form a first charge-accumulating path between the first beginning and the first ending, and there is no charge-accumulating path between the first beginning and the first ending other than the first path; and

a second synchronous element with a second beginning to receive a first phase and a second ending, the second synchronous element including;

a third transistor having an input terminal at the second beginning, an output terminal, and a gate coupled to receive the second phase;

a fourth transistor having an input terminal, an output terminal at the second ending, and a gate coupled to receive the first phase, in which the input terminal of the fourth transistor is connected to the output terminal of the third transistor at a second intermediate node so as to form a second charge-accumulating path between the second beginning and the second ending, and there is no charge-accumulating path between the second beginning and the second ending other than the second path; and

in which the second beginning is coupled to the first ending.

2. The rectifier of claim 1, in which

at least two of the plurality of stages are substantially identical.

3. The rectifier of claim 1, in which

the gate of the first transistor is coupled to the output terminal of one of the first and the second transistors to receive a DC bias voltage, in addition to being coupled to receive the first phase.

4. The rectifier of claim 3, in which

an amount of the DC bias voltage is a function of an amplitude of the RF signal.

5. The rectifier of claim 4, in which

the amount of the DC bias voltage is controlled such that an amount of an average current through the first transistor is substantially maximized for a given RF input power.

6. The rectifier of claim 1, in which

the gate of the second transistor is coupled to the input terminal of one of the first and the second transistors to receive a DC bias voltage, in addition to being coupled to receive the second phase.

7. The rectifier of claim 6, in which

an amount of the DC bias voltage is a function of an amplitude of the RF signal.

8. The rectifier of claim 7, in which

the amount of the DC bias voltage is controlled such that an amount of an average current through the first transistor is substantially maximized.

9. The rectifier of claim 1, in which

the first transistor and the second transistor are one of a PMOS-NMOS pair and NMOS-PMOS pair, respectively.

10. The rectifier of claim 1, in which

the first and second intermediate nodes are floating.

11. The rectifier of claim 1, in which

the first and second intermediate nodes are coupled together, and are floating together.

12. The rectifier of claim 1, in which

the first and second intermediate nodes are coupled together, and are coupled to ground.

13. A Radio Frequency Identification tag circuit, comprising:

a first antenna input node for receiving a first phase of an alternating RF wireless signal;

a second antenna input node for receiving a second phase of the alternating RF wireless signal which is substantially opposite to the first phase;

a plurality of serially coupled stages, at least one of the stages including;

a first synchronous element with a first beginning coupled to receive the second phase and a first ending, the first synchronous element including;

a first transistor having an input terminal at the first beginning, an output terminal, and a gate coupled to receive the first phase;

a second transistor having an input terminal, an output terminal at the first ending, and a gate coupled to receive the second phase, in which the input terminal of the second transistor is connected to the output terminal of the first transistor at a first intermediate node so as to form a first charge-accumulating path between the first beginning and the first ending, and there is no charge-accumulating path between the first beginning and the first ending other than the first path; and

a second synchronous element with a second beginning to receive the first phase and a second ending, the second synchronous element including;

a third transistor having an input terminal at the second beginning, an output terminal, and a gate coupled to receive the second phase;

a fourth transistor having an input terminal, an output terminal at the second ending, and a gate coupled to receive the first phase, in which the input terminal of the fourth transistor is connected to the output terminal of the third transistor at a second intermediate node so as to form a second charge-accumulating path between the second beginning and the second ending, and there is no charge-accumulating path between the second beginning and the second ending other than the second path; and

in which the second beginning is coupled to the first ending.

14. The RFID tag circuit of claim 13, in which

the transistors are one of PMOS transistors and NMOS transistors.

15. A rectifier for a Radio Frequency Identification tag circuit, comprising:

a first antenna input node for receiving a first phase of an alternating RF wireless signal;

a second antenna input node for receiving a second phase of the alternating RF wireless signal which is substantially opposite to the first phase;

a zeroth stage transistor having an input terminal connected to ground, an output terminal, and a gate coupled to receive the first phase;

a plurality of serially coupled stages, at least one of the stages including;

a first synchronous element with a first beginning coupled to receive the second phase and a first ending, the first synchronous element including;

a first transistor having an input terminal at the first beginning coupled to the output terminal of the zeroth stage transistor, an output terminal, and a gate coupled to receive the first phase;

a second transistor having an input terminal, an output terminal at the first ending, and a gate coupled to receive the second phase, in which the input terminal of the second transistor is connected to the output terminal of the first transistor at a first intermediate node so as to form a first charge-accumulating path between the first beginning and the first ending, and there is no charge-accumulating path between the first beginning and the first ending other than the first path; and

a second synchronous element with a second beginning to receive the first phase and a second ending, the second synchronous element including;

a third transistor having an input terminal at the second beginning, an output terminal, and a gate coupled to receive the second phase;

a fourth transistor having an input terminal, an output terminal at the second ending, and a gate coupled to receive the first phase, in which the input terminal of the fourth transistor is connected to the output terminal of the third transistor at a second intermediate node so as to form a second charge-accumulating path between the second beginning and the second ending, and there is no charge-accumulating path between the second beginning and the second ending other than the second path; and

in which the second beginning is coupled to the first ending.