Display device and method for manufacturing the same

• US 8,115,883 B2
• Filed: 08/23/2010
• Issued: 02/14/2012
• Est. Priority Date: 08/27/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Tsubuku, Masashi, Akimoto, Kengo, Hosoba, Miyuki, Sakakura, Masayuki, Oikawa, Yoshiaki
• Primary Examiner(s): Doan, Jennifer
• Application Number:
  US12/861,190
• Publication Number:
  US 20110049510A1
• Time in Patent Office: 540 Days
• Field of Search: 349/19, 349/33, 349/41, 349/42, 349/43, 349/49, 349/50
• US Class Current: 349/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Claims

1. A display device comprising:

a pixel portion over a substrate, comprising;

a first transistor comprising;

a first gate electrode layer;

a gate insulating layer over the first gate electrode layer;

a first source electrode layer and a first drain electrode layer which are over the gate insulating layer and partly overlap with the first gate electrode layer; and

a first oxide semiconductor layer which is over the gate insulating layer and partly overlaps with the first source electrode layer and the first drain electrode layer;

a first oxide insulating layer over the first source electrode layer, the first drain electrode layer, and the first oxide semiconductor layer;

a connection electrode layer which is over the first oxide insulating layer and electrically connected to the first drain electrode layer;

a second oxide insulating layer over the first oxide insulating layer and the connection electrode layer;

a protective insulating layer over the second oxide insulating layer; and

a pixel electrode layer which is over the protective insulating layer and electrically connected to the connection electrode layer,

a driver circuit portion over the substrate, comprising;

a second transistor comprising;

a second gate electrode layer;

the gate insulating layer over the second gate electrode layer;

a second oxide semiconductor layer over the gate insulating layer; and

a second source electrode layer and a second drain electrode layer which are over and partly overlap with the second oxide semiconductor layer;

the second oxide insulating layer over the second source electrode layer, the second drain electrode layer, and the second oxide semiconductor layer; and

the protective insulating layer over the second oxide insulating layer,

wherein the first gate electrode layer, the gate insulating layer, the first oxide semiconductor layer, the first source electrode layer, the first drain electrode layer, the first oxide insulating layer, the second oxide insulating layer, the protective insulating layer, and the pixel electrode layer each have a light-transmitting property.

2. The display device according to claim 1,

wherein the first gate electrode layer, the first source electrode layer, and the first drain electrode layer of the first transistor are formed using a metal oxide, and

wherein the second gate electrode layer, the second source electrode layer, and the second drain electrode layer of the second transistor are formed using a metal.

3. The display device according to claim 1, wherein the first gate electrode layer, the first source electrode layer, and the first drain electrode layer of the first transistor comprise indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, or zinc oxide.

4. The display device according to claim 1, wherein a planarization insulating layer having a light-transmitting property is formed between the second oxide insulating layer and the protective insulating layer in the pixel portion.

5. The display device according to claim 1, wherein a conductive layer is formed over the protective insulating layer which overlaps with the second oxide semiconductor layer in the driver circuit portion.

6. The display device according to claim 1, wherein the first oxide insulating layer and the second oxide insulating layer are formed using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride by a sputtering method.

7. The display device according to claim 1, further comprising an oxide conductive layer formed between the second oxide semiconductor layer and the second source electrode layer and between the second oxide semiconductor layer and the second drain electrode layer.

8. The display device according to claim 1, further comprising an oxide conductive layer formed between the second oxide semiconductor layer and the second source electrode layer and between the second oxide semiconductor layer and the second drain electrode layer wherein the oxide conductive layer comprises zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or gallium zinc oxide.

9. A method for manufacturing a display device comprising steps of:

forming a first gate electrode layer in a region to be a pixel portion;

forming a second gate electrode layer in a region to be a driver circuit portion;

forming a gate insulating layer over the first gate electrode layer and the second gate electrode layer;

forming a first transistor further comprising steps of;

forming a first source electrode layer and a first drain electrode layer which are over the gate insulating layer and partly overlap with the first gate electrode layer; and

forming a first oxide semiconductor layer which is over the gate insulating layer and partly overlaps with the first source electrode layer and the first drain electrode layer;

forming a second transistor further comprising steps of;

forming a second oxide semiconductor layer which is over the gate insulating layer and partly overlaps with the second gate electrode layer;

forming a first oxide insulating layer over the first oxide semiconductor layer; and

forming a second source electrode layer and a second drain electrode layer which are over the first oxide insulating layer and partly overlap with the second oxide semiconductor layer;

forming a connection electrode layer electrically connected to the first drain electrode layer;

forming a second oxide insulating layer over the first oxide insulating layer, the second oxide semiconductor layer, the second source electrode layer, and the second drain electrode layer;

forming a protective insulating layer over the second oxide insulating layer; and

forming a pixel electrode layer over the protective insulating layer in the region to be the pixel portion to be electrically connected to the connection electrode layer.

10. The method for manufacturing a display device according to claim 9, wherein the first gate electrode layer, the gate insulating layer, the first oxide semiconductor layer, the first source electrode layer, the first drain electrode layer, the first oxide insulating layer, the second oxide insulating layer, the protective insulating layer, and the pixel electrode layer each have a light-transmitting property.

11. The method for manufacturing a display device according to claim 9, wherein a planarization insulating layer is formed between the second oxide insulating layer and the protective insulating layer in the region to be the pixel portion.

12. The method for manufacturing a display device according to claim 9, wherein a conductive layer is formed over the protective insulating layer which overlaps with the second oxide semiconductor layer in the region to be the driver circuit portion.