Phase change memory devices and systems, and related programming methods
First Claim
1. A method of writing data in a phase change memory cell in a memory, the memory comprising a plurality of phase change memory cells, and the method comprising:
- receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells;
sensing data stored in the selected phase change memory cell;
determining whether or not the sensed data is equal to the write data; and
if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.
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Abstract
A method of writing data in a phase change memory includes receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.
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Citations
39 Claims
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1. A method of writing data in a phase change memory cell in a memory, the memory comprising a plurality of phase change memory cells, and the method comprising:
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receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells; sensing data stored in the selected phase change memory cell; determining whether or not the sensed data is equal to the write data; and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory device comprising:
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a memory array comprising a plurality of phase change memory cells configured to store write data; and a generator configured to generate a level-controlled write current and apply the level-controlled write current to the memory array to iteratively apply the level-controlled write current to a selected phase change memory cell in the plurality of phase change memory cells, wherein the level-controlled write current is adjusted with each iterative application of the level-controlled write current, until a resistive state of the selected phase change memory cell falls within a defined resistance distribution corresponding to the write data. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A memory device comprising:
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an array of phase change memory cells divided into a first memory block including a first selected memory cell and a second memory block including a second selected memory cell; sensing and writing circuitry configured to simultaneously write the first and second selected memory cells with write data by iteratively applying a level-controlled write current to the first and second selected memory cells, and performing a verify-read operation on the first and second selected memory cells until respective programmed states for the first and second memory cells are equal to the write data. - View Dependent Claims (29, 30)
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31. A method of writing data to a memory comprising a plurality phase change memory cells each storing N-bit data according to respectively corresponding N2 resistance distributions, the method comprising:
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receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells; applying a write current to the selected phase change memory cell, wherein the write current is defined in relation to the write data; after applying the write current, sensing a resistive state of the selected phase change memory cell; comparing the sensed resistive state of the selected phase change memory cell to a reference defined in relation to the write data; and if the sensed resistive state fails comparison with the reference, adjusting the write current, and applying the adjusted write current to the selected phase change memory cell. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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Specification