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Method and circuit for erasing a non-volatile memory cell

  • US 8,116,142 B2
  • Filed: 09/06/2005
  • Issued: 02/14/2012
  • Est. Priority Date: 09/06/2005
  • Status: Active Grant
First Claim
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1. A method of erasing a subset of non-volatile memory cells (“

  • NVM”

    ) within a column segment of NVM cells having a first bit-line connected a first terminal of the NVM cells and a second bit line connected to the second terminal of the NVM cells, said method comprising;

    shunting through a shunting element the first bit-line to the second bit-line substantially concurrently to applying an erase voltage to a gate terminal of the subset of NVM cells to be erased.

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