Method and circuit for erasing a non-volatile memory cell

• US 8,116,142 B2
• Filed: 09/06/2005
• Issued: 02/14/2012
• Est. Priority Date: 09/06/2005
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG, Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Riedel, Stephan, Eitan, Boaz
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US11/220,872
• Publication Number:
  US 20070058444A1
• Time in Patent Office: 2,352 Days
• Field of Search: 365/185.29, 365/185.33
• US Class Current: 365/185.29
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.

Claims

1. A method of erasing a subset of non-volatile memory cells (“

NVM”

) within a column segment of NVM cells having a first bit-line connected a first terminal of the NVM cells and a second bit line connected to the second terminal of the NVM cells, said method comprising;

shunting through a shunting element the first bit-line to the second bit-line substantially concurrently to applying an erase voltage to a gate terminal of the subset of NVM cells to be erased.

2. The method according to claim 1, wherein shunting the first bit-line to the second bit-line includes activating a shunting element located on the same column as the sub-set of cells.

3. The method according to claim 1, wherein shunting the first bit-line to the second bit-line includes activating a shunting element located outside the same column as the sub-set of cells.

4. The method according to claim 3, further comprising electrically connecting the shunting element located outside the same column as the sub-set of cells with the same column as the sub-set of cells through one or more select transistors.