Read only memory and method of reading same

• US 8,116,153 B2
• Filed: 01/14/2010
• Issued: 02/14/2012
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rana, Manmohan, Maiti, Bikas, Sharma, Ashish
• Primary Examiner(s): DINH, SON T
• Application Number:
  US12/687,847
• Publication Number:
  US 20100208506A1
• Time in Patent Office: 761 Days
• Field of Search: 365/189.16, 365/203, 365/204, 365/189.02, 365/189.14
• US Class Current: 365/189.16
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time.

Claims

1. A Read Only Memory (ROM) device operating at a supply voltage, comprising:

a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage;

a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines;

a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage;

one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines;

one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise;

a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (n-MOSFET) of the plurality of transmission gates;

an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line, wherein the pull-down bit line signal operates at the level shifted voltage; and

a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation.

2. The ROM device of claim 1, wherein the control circuit generates a row address signal for enabling the row address decoder.

3. The ROM device of claim 1, wherein the inverter circuit comprises one or more inverters.

4. The ROM device of claim 1, wherein each of the one or more column multiplexers comprises a pull-up transistor connected to the plurality of bit lines and wherein the pull-up bit line signal is provided to a gate terminal of the pull-up transistor for pre-charging the plurality of bit lines.

5. The ROM device of claim 4, wherein the pull-up transistor is a p-channel metal oxide semiconductor field effect transistor (PMOSFET).

6. The ROM device of claim 1, wherein each of the one or more column multiplexers comprises a pull-down transistor connected to a corresponding bit line of the plurality of bit lines and the control circuit, and wherein the pull-down bit line signal is provided to a gate terminal of the plurality of pull-down transistors for discharging the enabled one of the plurality of bit lines.

7. The ROM device of claim 6, wherein the pull-down transistor is a NMOSFET.

8. A Read Only Memory (ROM) device operating at a supply voltage, comprising:

a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage;

a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines;

a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage;

one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines;

one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise;

a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (NMOSFET) of the plurality of transmission gates;

an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line; and

a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, the one or more sense amplifiers performing the read operation.

9. The ROM device of claim 8, wherein at least one of the pull-down bit line signal, the pull-up bit line signal and the sense amplifier enable signal operate at the level shifted voltage.

10. The ROM device of claim 8, wherein the control circuit generates a row address signal for enabling the row address decoder.

11. The ROM device of claim 8, wherein the inverter circuit comprises one or more inverters.

12. The ROM device of claim 8, wherein each of the one or more column multiplexers comprises a pull-up transistor connected to the plurality of bit lines and wherein the pull-up bit line signal is provided to a gate terminal of the pull-up transistor for pre-charging the plurality of bit lines.

13. The ROM device of claim 12, wherein the pull-up transistor is a p-channel metal oxide semiconductor field effect transistor (p-MOSFET).

14. The ROM device of claim 8, wherein each of the one or more column multiplexers comprises a pull-down transistor connected to a corresponding bit line of the plurality of bit lines and the control circuit, and wherein the pull-down bit line signal is provided to a gate terminal of the plurality of pull-down transistors for discharging the enabled one of the plurality of bit lines.

15. The ROM device of claim 14, wherein the pull-down transistor is the n-MOSFET.

16. A method for operating a Read Only Memory (ROM) device, the ROM operating at a supply voltage and including a ROM array, the ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, the method comprising the steps of:

generating a column address signal for enabling at least one of the plurality of bit lines, wherein the column address signal operates at a level shifted voltage that is higher than the supply voltage;

generating a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage;

disabling the pull-up bit line signal based on the plurality of bit lines being pre-charged to a first predefined threshold voltage;

generating a row address signal for selecting at least one of the plurality of word lines for a read operation, wherein the plurality of word lines operate at the level shifted voltage;

enabling one or more sense amplifiers associated with each of the plurality of bit lines by a sense amplifier enable signal, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation;

generating a pull-down bit line signal by disabling the column address signal, wherein the pull-down bit line signal discharges the enabled one of the plurality of bit lines, and wherein the pull-down bit line signal operates at the level shifted voltage; and

disabling the selected one of the plurality of word lines by disabling the row address signal for completing the read operation.

17. The method for performing a read operation in a ROM device of claim 16, wherein disabling the column address signal comprises inverting the column address signal for completing the read operation.

18. The method for performing a read operation in a ROM device of claim 16, further comprising providing the pull-up bit line signal to a gate terminal of a pull-up transistor for pre-charging the plurality of bit lines to the supply voltage.

19. The method for performing a read operation in a ROM device of claim 16, further comprising providing the pull-down bit line signal to a gate terminal of a pull-down transistor for discharging the plurality of bit lines.