System and method for memory hub-based expansion bus
First Claim
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1. A computer system, comprising:
- a processor coupled to a processor bus;
a system controller coupled to the processor through the processor bus, the system controller having a peripheral device port, the system controller further comprising a memory hub controller coupled to a system memory port and adapted to provide memory command packets including information to access memory devices;
a plurality of memory modules each having a plurality of memory devices coupled to a memory hub, the memory hub adapted to receive memory command packets and access the memory devices according to the memory command packets and further adapted to provide memory responses in response thereto wherein the memory modules are coupled to the system controller via a controller/hub interface comprising at least one controller/hub interface bus and wherein the plurality of memory modules are coupled to the controller/hub interface bus;
a first portion of a memory bus coupled to the system memory port and the memory hub on which the memory command packets from the memory hub controller are provided to the memory hub of the memory module and memory responses are provided to the memory hub controller;
an expansion module having a processor circuit adapted to provide memory command packets including information to access the memory devices of the memory module and further adapted to process data included in the memory responses from the memory hub of the memory module; and
a second portion of the memory bus coupled to the memory hub of the memory module and the processor circuit of the expansion module on which the memory command packets from the processor circuit are provided to the memory hub of the memory module and memory responses are provided to the processor circuit.
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Abstract
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
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Citations
24 Claims
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1. A computer system, comprising:
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a processor coupled to a processor bus; a system controller coupled to the processor through the processor bus, the system controller having a peripheral device port, the system controller further comprising a memory hub controller coupled to a system memory port and adapted to provide memory command packets including information to access memory devices; a plurality of memory modules each having a plurality of memory devices coupled to a memory hub, the memory hub adapted to receive memory command packets and access the memory devices according to the memory command packets and further adapted to provide memory responses in response thereto wherein the memory modules are coupled to the system controller via a controller/hub interface comprising at least one controller/hub interface bus and wherein the plurality of memory modules are coupled to the controller/hub interface bus; a first portion of a memory bus coupled to the system memory port and the memory hub on which the memory command packets from the memory hub controller are provided to the memory hub of the memory module and memory responses are provided to the memory hub controller; an expansion module having a processor circuit adapted to provide memory command packets including information to access the memory devices of the memory module and further adapted to process data included in the memory responses from the memory hub of the memory module; and a second portion of the memory bus coupled to the memory hub of the memory module and the processor circuit of the expansion module on which the memory command packets from the processor circuit are provided to the memory hub of the memory module and memory responses are provided to the processor circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system, comprising:
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a processor having a processor bus; a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a memory hub controller coupled to a system memory port and adapted to provide memory command packets including information to access memory devices; first and second memory modules, each memory module having a respective plurality of memory devices and a respective memory hub coupled to the respective plurality of memory devices, the respective memory hubs adapted to receive memory requests for accessing memory locations in the respective plurality of memory devices and provide memory responses in response to receiving the memory requests; first and second expansion modules, each expansion module having a respective processor circuit adapted to provide memory requests to the memory hubs to access memory locations in the respective plurality of memory devices and receive memory responses from the memory hubs wherein the expansion modules are coupled to the memory modules in series; a memory hub controller adapted to provide memory requests to the memory modules to the memory hubs to access memory locations in the respective plurality of memory devices and receive memory responses from the memory hubs, the memory hub controller comprising a controller/hub interface comprising at least one memory bus; and the memory bus coupled to the first and second memory hubs, the first and second processor circuits and the system memory port, the memory bus configured to couple memory requests to the memory modules and couple memory responses to the memory hub controller and the first and second processor circuits. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An electronic device, comprising:
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a processor having a processor bus; a memory hub controller coupled to the processor bus wherein the memory hub controller comprises a controller/hub interface comprising at least one controller/hub interface bus; a plurality of memory modules, each of the memory modules having a plurality of memory devices coupled to the respective memory hub and configured to issue local memory requests in response to memory requests issued by the memory hub controller to only the memory devices coupled to the memory hub and provide memory responses to the memory hub controller via the at least one controller hub interface bus; an expansion module having a processor unit coupled to at least one of the memory modules in a series arrangement, the expansion module further having a plurality of memory devices coupled to the processor unit and configured to provide memory responses to the processor unit responsive to receiving memory requests from the processor unit, the processor unit configured to provide memory requests to and receive memory responses from at least one of the memory devices of the at least one of the memory modules. - View Dependent Claims (21, 22, 23, 24)
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Specification