Flash memory control devices that support multiple memory mapping schemes and methods of operating same

• US 8,117,374 B2
• Filed: 11/29/2005
• Issued: 02/14/2012
• Est. Priority Date: 02/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jin-Hyuk, Choi, Young-Joon, Park, Chan-Ik
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US11/289,175
• Publication Number:
  US 20060179212A1
• Time in Patent Office: 2,268 Days
• Field of Search: 711/100, 711102-103, 711/115, 711/156, 711202-203
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control

Abstract

There is provided an apparatus for controlling a flash memory, which includes a memory for storing a plurality of flash translation layers; and a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer.

Claims

1. A flash memory control device, comprising:

a memory unit configured to store a plurality of flash translation layers; and

a control unit electrically coupled to said memory unit, said control unit configured to select one of the plurality of flash translation layers in response to determining a pattern of flash memory access associated with at least one applied memory access request and further configured to manage mapping of data to a flash memory device based on the selected one of the plurality of flash translation layers;

wherein the plurality of flash translation layers map logical addresses and physical addresses differently according to different quantities of data being written into the flash memory device.

2. The flash memory control device of claim 1, wherein said control unit is further configured to extract logical address information from data applied to the flash memory control device with the at least one applied memory access request;

wherein determining a pattern of flash memory access includes determining a pattern of flash memory access from the extracted logical address information; and

wherein said control unit is configured to select a page mapping scheme in response to a single write request and a log mapping scheme in response to a sequential write request.

3. The flash memory control device of claim 1, wherein said control unit is further configured to accumulate access information from the at least one applied memory access request;

and wherein determining a pattern of flash memory access includes determining a pattern of flash memory access using the accumulated access information.

4. The flash memory control device of claim 1, wherein each of the plurality of flash translation layers maps to a respective memory region within the flash memory device.

5. The flash memory control device of claim 1, wherein a first one of the plurality of flash translation layers corresponds to a page mapping scheme and a second one of the plurality of flash translation layers corresponds to mapping scheme selected from a group consisting of a log mapping scheme and a block mapping scheme.

6. The flash memory control device of claim 1, wherein said memory unit and said control unit are packaged within a flash memory card.

7. The flash memory control device of claim 1, wherein said memory unit and said control unit are packaged within a solid state disk controller.

8. The flash memory control device of claim 1, wherein said memory unit and said control unit are contained within an xD card.

9. The flash memory control device of claim 1, wherein relatively small quantities of data being written into the flash memory device include a file allocation table (FAT).

10. A flash memory control device, comprising:

a memory unit configured to store a plurality of flash translation layers; and

a control unit electrically coupled to said memory unit, said control unit configured to select one of the plurality of flash translation layers in response to extracting logical address information from data received by the flash memory control device and determining a pattern of flash memory access from the extracted logical address information;

wherein the plurality of flash translation layers map logical addresses and physical addresses differently according to different quantities of data being written into a flash memory device.

11. The flash memory control device of claim 10, wherein said control unit is further configured to manage mapping of data to the flash memory device based on the selected one of the plurality of flash translation layers.

12. An apparatus for controlling a flash memory, comprising:

a memory for storing a plurality of flash translation layers; and

a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer;

wherein the plurality of flash translation layers map logical addresses and physical addresses differently according to different quantities of data being written into the flash memory.

13. The apparatus of claim 12, wherein the control block extracts logical address information from data inputted when the access is requested and determining the pattern of access based on the extracted logical address information.

14. The apparatus of claim 12, wherein the control block accumulates the access pattern information when the access, is requested, and determines the access pattern of the flash memory based on the accumulated access pattern information.

15. The apparatus of claim 12, wherein the control block determines the access pattern based on access information inputted from outside when the access is requested.

16. The apparatus of claim 12, wherein the flash memory includes a plurality of memory regions corresponding to the flash translation layers individually, and mapping data of each memory region are managed by a corresponding flash translation layer.

17. The apparatus of claim 12, wherein the flash memory is divided into at least a first memory region and a second memory region, and the memory includes a first flash translation layer for managing mapping data of the first memory region and a second flash translation layer for managing mapping data of the second memory region.

18. The apparatus of claim 17, wherein the first flash translation layer uses a page mapping scheme, and the second flash translation layer uses any one of log and block mapping schemes.

19. The apparatus of claim 12, wherein the apparatus for controlling the flash memory is included in a memory card.

20. The apparatus of claim 12, wherein the apparatus for controlling the flash memory is included in a semiconductor solid state disk controller.

21. A flash memory system, comprising:

a host;

a flash memory including a plurality of memory regions; and

a control device storing at least two flash translation layers;

wherein when an access is requested from the host, the control device determines a pattern of the access based on access information provided from the host, selects one of the flash translation layers based on the determined access pattern, and manages mapping data for the memory regions in the flash memory based on the selected flash translation layer;

wherein the at least two flash translation layers map logical addresses and physical addresses differently according to different quantities of data being written into the flash memory.

22. The flash memory system of claim 21, wherein the control device includes:

a memory for storing the flash translation layers; and

a control block for determining the pattern of the access based on the access information, selecting one of the flash translation layers based on the determined access pattern, and managing mapping data for the memory regions of the flash memory based on the selected flash translation layer.

23. The flash memory system of claim 22, wherein the control block extracts logical address information from data inputted when the access is requested and determining the pattern of access based on the extracted logical address information.

24. The flash memory system of claim 22, wherein the control block accumulates the access pattern information when the access is requested, and determines the access pattern of the flash memory based on the accumulated access pattern information.

25. The flash memory system of claim 22, wherein the control block determines the access pattern based on access information inputted from outside when the access is requested.

26. The flash memory system of claim 22, wherein, among the flash translation layers, the first flash translation layer uses a page mapping scheme, and the second flash translation layer uses any one of log and block mapping schemes.

27. The flash memory system of claim 26, wherein among the memory regions, mapping data of some memory regions are managed by the first flash translation layer and mapping data of the other regions are managed by the second flash translation layer.

28. The flash memory system of claim 22, wherein the flash memory and the control device form a memory card.

29. The flash memory system of claim 22, wherein the flash memory system is a semiconductor solid state disk controller.

30. A method for managing mapping data of a flash memory, comprising:

when an access to the flash memory is requested, determining a pattern of the access;

selecting one of multiple flash translation layers based on the determined access pattern; and

managing mapping data of the flash memory based on the selected flash translation layer;

wherein the multiple flash translation layers map logical addresses and physical addresses differently according to different quantities of data being written into the flash memory.

31. The method of claim 30, wherein the determining the pattern of the access includes:

extracting logical address information from data inputted when the access is requested; and

determining the pattern of the requested access based on the extracted logical address information.

32. The method of claim 30, wherein the determining the pattern of the access includes:

accumulating access pattern information when the access is requested; and

determining the pattern of the access to the flash memory based on the accumulated access pattern information.

33. The method of claim 30, wherein the access pattern is determined based on access information inputted from outside when the access is requested.

34. A flash memory control device, comprising:

a memory unit configured to store a plurality of flash translation layers; and

a control unit electrically coupled to said memory unit, said control unit configured to select one of the plurality of flash translation layers in response to determining a pattern of flash memory access associated with at least one applied memory access request and further configured to manage mapping of data to a flash memory device based on the selected one of the plurality of flash translation layers;

wherein the plurality of flash translation layers map logical addresses and physical addresses in different manners in terms of a mapping unit or a position of the physical addresses.