Noise reduction by returning to normal mode upon above threshold usage while periodically changing between sleep mode and low frequency mode
First Claim
1. A noise reduction apparatus of a dynamic power management processor, the apparatus comprising:
- a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and
a power supply unit configured to supply a voltage corresponding to the operation mode set by the mode setting unit,wherein the mode setting unit is configured to change the operation mode of the processor periodically between a sleep mode and a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor,wherein the low frequency mode includes a low frequency mode voltage and a low frequency mode clock frequency respectively lower than a general mode voltage and a general mode clock frequency and respectively higher than a sleep mode voltage and a sleep mode clock frequency, andwherein, if usage of the processor is higher than a certain value while the operation mode is periodically changed between the sleep mode and the low frequency mode, the operation mode returns to a general operation mode.
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Abstract
A noise reduction apparatus and method of a processor to which a dynamic power management technique is applied. The noise reduction apparatus includes a mode setting unit for detecting a use state of a processor and setting an operation mode; and a power supply unit for supplying voltage corresponding to the operation mode set by the mode setting unit. The operation mode includes a general mode in which the processor normally operates; a sleep mode in which activity of the processor is suspended; and a low frequency mode in which the processor operates at voltage and clock frequency lower than those of the general mode and higher than those of the sleep mode. The mode setting unit changes between the general mode and the sleep mode, wherein the processor is set to the low frequency mode as an intermediate step.
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Citations
8 Claims
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1. A noise reduction apparatus of a dynamic power management processor, the apparatus comprising:
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a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and a power supply unit configured to supply a voltage corresponding to the operation mode set by the mode setting unit, wherein the mode setting unit is configured to change the operation mode of the processor periodically between a sleep mode and a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor, wherein the low frequency mode includes a low frequency mode voltage and a low frequency mode clock frequency respectively lower than a general mode voltage and a general mode clock frequency and respectively higher than a sleep mode voltage and a sleep mode clock frequency, and wherein, if usage of the processor is higher than a certain value while the operation mode is periodically changed between the sleep mode and the low frequency mode, the operation mode returns to a general operation mode. - View Dependent Claims (2, 3, 4)
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5. A noise reduction method of a dynamic power management processor by an apparatus, comprising the steps of:
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(A) detecting, by the apparatus, a use state of a processor and setting an operation mode of the processor; (B) setting, by the apparatus, the operation mode of the processor to a sleep mode in response to the detected use state of the processor; (C) changing the operation mode of the processor periodically between the sleep mode and a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor; and (D) if usage of the processor is higher than a certain value while the operation mode is periodically changed between the sleep mode and the low frequency mode, returning the operation mode to a general operation mode by the apparatus, wherein the low frequency mode is a mode having at a low frequency mode voltage and a low frequency mode clock frequency respectively lower than a general mode voltage and a general mode clock frequency and respectively higher than a sleep mode voltage and a sleep mode clock frequency. - View Dependent Claims (6, 7, 8)
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Specification