Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein

• US 8,117,580 B1
• Filed: 08/23/2007
• Issued: 02/14/2012
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/895,132
• Time in Patent Office: 1,636 Days
• Field of Search: 716/111, 716/116, 716/136
• US Class Current: 716/116
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates. When separate test bitstreams are used, the configuration procedure programs the IC with an associated user bitstream before terminating.

Claims

1. An article of manufacture, comprising:

a non-transitory computer-readable storage medium encoded with a set of configuration bitstreams for programming an integrated circuit (IC) comprising a plurality of programmable resources, wherein;

each of the configuration bitstreams implements a particular design on a respective subset of the programmable resources, and each of the configuration bitstreams is a different implementation of the particular design; and

each of the programmable resources is excluded from at least one of the respective subsets of programmable resources used by at least one of the configuration bitstreams.

2. The article of manufacture of claim 1, wherein each of the configuration bitstreams includes at least one common subset of the programmable resources, and wherein logic implemented by the common subset is implemented using triple modular redundancy.

3. The article of manufacture of claim 1, wherein each configuration bitstream enables the particular design to meet a common set of predetermined timing constraints when programmed into a fully functional IC.

4. The article of manufacture of claim 1 wherein the set of configuration bitstreams resides in a single memory device.

5. The article of manufacture of claim 4 wherein the memory device comprises a programmable read-only memory (PROM).

6. The article of manufacture of claim 1 wherein at least one of the configuration bitstreams is a partial configuration bitstream.

7. The article of manufacture of claim 1 wherein the IC comprises a programmable logic device (PLD).

8. The article of manufacture of claim 7 wherein the PLD comprises a field programmable gate array (FPGA).