System and method for detecting in-line synchronization primitives in binary applications

• US 8,117,600 B1
• Filed: 12/29/2005
• Issued: 02/14/2012
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: Veritas Technologies, LLC (Whitehouse Group Ltd.)
• Original Assignee: Symantec Operating Corporation (Gen Digital Inc.)
• Inventors: Roeck, Guenter E., Shats, Serge
• Primary Examiner(s): Dam, Tuan
• Assistant Examiner(s): Aguilera, Todd
• Application Number:
  US11/321,460
• Time in Patent Office: 2,238 Days
• Field of Search: 717/127, 712/108, 712/216, 710/200, 707/8, 711/147
• US Class Current: 717/128
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3644 by instrumenting at runtime
• CPC Class Codes: G06F 9/45525 Optimisation or modification within the same instruction set architecture, e.g. HP Dynamo

Abstract

A system, method, and computer-accessible medium are disclosed for identifying in-line synchronization instructions in binary program code. One or more executable segments of the binary program code may be scanned to identify one or more potential in-line synchronization instructions. For each potential in-line synchronization instruction, it may be determined whether neighboring potential instructions are valid instructions. For each potential in-line synchronization instruction, it may be determined that the potential in-line synchronization instruction is a valid in-line synchronization instruction if the neighboring potential instructions are valid instructions.

Claims

1. A computer-implemented method for identifying in-line synchronization instructions in binary program code, the method comprising:

performing by a computer;

scanning one or more executable segments of the binary program code to identify one or more potential in-line synchronization instructions; and

determining whether each of the one or more potential in-line synchronization instructions is non-executable data or a valid in-line synchronization instruction, comprising, for each potential in-line synchronization instruction;

determining whether each respective one of a plurality of neighboring potential instructions is a valid instruction or non-executable data, wherein the plurality of neighboring potential instructions are located in a segment of the binary program code including the respective potential in-line synchronization instruction;

determining that the respective potential in-line synchronization instruction is a valid in-line synchronization instruction in response to determining that all of the plurality of neighboring potential instructions in the segment are valid instructions; and

determining that the respective potential in-line synchronization instruction is non-executable data in response to determining that one or more of the neighboring potential instructions in the segment are valid instructions and one or more of the neighboring potential instructions occurring prior to the one or more valid instructions in the segment are non-executable data.

2. The method of claim 1,

wherein a target processor for execution of the binary program code is configured to execute variable-length instruction words;

wherein identifying the one or more potential in-line synchronization instructions comprises determining that each of the one or more potential in-line synchronization instructions is within a graph of possible instructions for a corresponding candidate phrase in the binary program code.

3. The method of claim 1, further comprising:

performing by a computer;

for each valid in-line synchronization instruction;

setting a breakpoint in the binary program code;

evaluating an instruction data address when the breakpoint is encountered in execution of the binary program code; and

determining that the in-line synchronization instruction corresponding to the breakpoint is not a valid in-line synchronization instruction if the instruction data address is not in a shared memory segment.

4. The method of claim 1, further comprising:

performing by a computer;

setting a breakpoint in the binary program code for each of the potential in-line synchronization instructions;

setting page protection for affected memory pages to exec only, wherein a target processor for execution of the binary program code is configured with separate read and exec page protection;

if a page access error occurs regarding a read on an address with one of the breakpoints, determining that the access is unrelated to an in-line synchronization instruction; and

if one of the breakpoints is executed, determining that the potential in-line synchronization instruction corresponding to the executed breakpoint is a valid in-line synchronization instruction.

5. The method of claim 1,

wherein determining whether neighboring potential instructions are valid instructions comprises following branches recursively to determine whether subsequent potential instructions are valid instructions.

6. A non-transitory, computer-accessible storage medium comprising program instructions for identifying in-line synchronization instructions in binary program code, wherein the program instructions are computer-executable to implement:

scanning one or more executable segments of the binary program code to identify one or more potential in-line synchronization instructions; and

determining whether each of the one or more potential in-line synchronization instructions is non-executable data or a valid in-line synchronization instruction, comprising, for each potential in-line synchronization instruction;

determining whether each respective one of a plurality of neighboring potential instructions is a valid instruction or non-executable data, wherein the plurality of neighboring potential instructions are located in a segment of the binary program code including the respective potential in-line synchronization instruction;

determining that the respective potential in-line synchronization instruction is a valid in-line synchronization instruction in response to determining that all of the plurality of neighboring potential instructions are valid instructions; and

determining that the respective potential in-line synchronization instruction is non-executable data in response to determines that one or more of the neighboring potential instructions in the segment are valid instructions and one or more of the neighboring potential instructions occurring prior to the one or more valid instructions in the segment are non-executable data.

7. The non-transitory, computer-accessible storage medium of claim 6,

wherein a target processor for execution of the binary program code is configured to execute variable-length instruction words;

wherein identifying the one or more potential in-line synchronization instructions comprises determining that each of the one or more potential in-line synchronization instructions is within a graph of possible instructions for a corresponding candidate phrase in the binary program code.

8. The non-transitory, computer-accessible storage medium of claim 6, wherein the program instructions are further computer-executable to implement:

for each valid in-line synchronization instruction;

setting a breakpoint in the binary program code;

evaluating an instruction data address when the breakpoint is encountered in execution of the binary program code; and

determining that the in-line synchronization instruction corresponding to the breakpoint is not a valid in-line synchronization instruction if the instruction data address is not in a shared memory segment.

9. The non-transitory, computer-accessible storage medium of claim 6, wherein the program instructions are further computer-executable to implement:

setting a breakpoint in the binary program code for each of the potential in-line synchronization instructions;

setting page protection for affected memory pages to exec only, wherein a target processor for execution of the binary program code is configured with separate read and exec page protection;

if a page access error occurs regarding a read on an address with one of the breakpoints, determining that the access is unrelated to an in-line synchronization instruction; and

if one of the breakpoints is executed, determining that the potential in-line synchronization instruction corresponding to the executed breakpoint is a valid in-line synchronization instruction.

10. A system comprising:

a processor; and

a memory coupled to the processor, wherein the memory stores program instructions which are executable by the processor to;

scan one or more executable segments of binary program code to identify one or more potential in-line synchronization instructions; and

determine whether each of the one or more potential in-line synchronization instructions is non-executable data or a valid in-line synchronization instruction, wherein, for each potential in-line synchronization instruction, the program instructions are executable by the processor to;

determine whether each respective one of a plurality of neighboring potential instructions is a valid instruction or non-executable data, wherein the plurality of neighboring potential instructions are located in a segment of the binary program code including the respective potential in-line synchronization instruction;

determine that the respective potential in-line synchronization instruction is a valid in-line synchronization instruction in response to determining that all of the plurality of neighboring potential instructions in the segment are valid instructions; and

determine that the respective potential in-line synchronization instruction is non-executable data in response to determining that one or more of the neighboring potential instructions in the segment are valid instructions and one or more of the neighboring potential instructions occurring prior to the one or more valid instructions in the segment are non-executable data.

11. The system of claim 10,

wherein a target processor for execution of the binary program code is configured to execute variable-length instruction words;

wherein in identifying the one or more potential in-line synchronization instructions, the program instructions are further executable by the processor to determine that each of the one or more potential in-line synchronization instructions is within a graph of possible instructions for a corresponding candidate phrase in the binary program code.

12. The system of claim 10, wherein the program instructions are further executable by the processor to:

for each valid in-line synchronization instruction;

set a breakpoint in the binary program code;

evaluate an instruction data address when the breakpoint is encountered in execution of the binary program code; and

determine that the in-line synchronization instruction corresponding to the breakpoint is not a valid in-line synchronization instruction if the instruction data address is not in a shared memory segment.

13. The system of claim 10, wherein the program instructions are further executable by the processor to:

set a breakpoint in the binary program code for each of the potential in-line synchronization instructions;

set page protection for affected memory pages to exec only, wherein a target processor for execution of the binary program code is configured with separate read and exec page protection;

if a page access error occurs regarding a read on an address with one of the breakpoints, determine that the access is unrelated to an in-line synchronization instruction; and

if one of the breakpoints is executed, determine that the potential in-line synchronization instruction corresponding to the executed breakpoint is a valid in-line synchronization instruction.