Thin film transistor and method for manufacturing the same

• US 8,119,468 B2
• Filed: 04/14/2009
• Issued: 02/21/2012
• Est. Priority Date: 04/18/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyairi, Hidekazu, Dairiki, Koji, Egi, Yuji, Jinbo, Yasuhiro, Isa, Toshiyuki
• Primary Examiner(s): Nguyen, Khiem D
• Assistant Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US12/423,123
• Publication Number:
  US 20090261328A1
• Time in Patent Office: 1,043 Days
• Field of Search: 438/151, 438/158, 257/57, 257/E21.412
• US Class Current: 438/158
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/4404 Coatings or surface treatment on the inside of the reaction chamber or on parts thereof
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.

Claims

1. A method for manufacturing a thin film transistor, the method comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode, the gate insulating layer comprising silicon nitride;

exposing the gate insulating layer to plasma generated by a gas containing nitrogen;

forming a semiconductor layer over the gate insulating layer by using a mixed gas comprising a semiconductor material gas and a nitrogen-containing gas, wherein a concentration of the nitrogen-containing gas is reduced during the formation of the semiconductor layer;

forming source and drain regions over the semiconductor layer wherein the source and drain regions comprise a semiconductor and an impurity imparting one conductivity type to the semiconductor; and

forming source and drain electrodes over the source and drain regions, respectively.

2. The method according to claim 1,

wherein the gas containing nitrogen is an ammonia gas.

3. The method according to claim 1,

wherein the gas containing nitrogen is a mixed gas containing an ammonia gas and a hydrogen gas.

4. The method according to claim 1,

wherein the mixed gas further comprises a diluent gas.

5. The method according to claim 1,

wherein the mixed gas further comprises a diluent gas, and

wherein the semiconductor material gas is selected from a silicon hydride gas, a silicon fluoride gas, and a silicon chloride gas.

6. The method according to claim 1,

wherein the mixed gas further comprises a diluent gas, and

wherein the diluent gas is selected from a hydrogen gas, a nitrogen gas, and an ammonia gas.

7. The method according to claim 1,

wherein the gate insulating layer has a stacked structure in which a silicon oxynitride layer is stacked over a silicon nitride layer.

8. The method according to claim 1, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride, and

wherein the exposure of the gate insulating layer to plasma is performed after forming the second gate insulating layer.

9. The method according to claim 1, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride and has a thickness greater than or equal to 1 nm and less than or equal to 3 nm.

10. A method for manufacturing a thin film transistor, the method comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode in a treatment chamber, the gate insulating layer comprising silicon nitride;

exposing the gate insulating layer to plasma generated by a gas containing nitrogen;

removing the substrate from the treatment chamber;

coating an inner wall of the treatment chamber with silicon nitride;

providing the substrate into the treatment chamber;

forming a semiconductor layer over the gate insulating layer in the treatment chamber by using a mixed gas comprising a semiconductor material gas and a nitrogen-containing gas, wherein a concentration of the nitrogen-containing gas is reduced during the formation of the semiconductor layer;

forming source and drain regions over the semiconductor layer wherein the source and drain regions comprise a semiconductor and an impurity imparting one conductivity type to the semiconductor; and

forming source and drain electrodes over the source and drain regions, respectively.

11. The method according to claim 10 further comprising a step of cleaning the treatment chamber,

wherein the cleaning of the treatment chamber is performed after removing the substrate from the treatment chamber and before providing the substrate into the treatment chamber.

12. The method according to claim 10 further comprising a step of exposing the gate insulating layer to an ammonia gas.

13. The method according to claim 10 further comprising a step of exposing the gate insulating layer to a mixed gas containing an ammonia gas and a hydrogen gas.

14. The method according to claim 10,

wherein the mixed gas further comprises a diluent gas.

15. The method according to claim 10,

wherein the mixed gas further comprises a diluent gas, and

wherein the semiconductor material gas is selected from a silicon hydride gas, a silicon fluoride gas, and a silicon chloride gas.

16. The method according to claim 10,

wherein the mixed gas further comprises a diluent gas, and

wherein the diluent gas is selected from a hydrogen gas, a nitrogen gas, and an ammonia gas.

17. The method according to claim 10,

wherein the gate insulating layer has a stacked structure in which a silicon oxynitride layer is stacked over a silicon nitride layer.

18. The method according to claim 10, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride, and

wherein the exposure of the gate insulating layer to plasma is performed after forming the second gate insulating layer.

19. The method according to claim 10, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride and has a thickness greater than or equal to 1 nm and less than or equal to 3 nm.

20. A method for manufacturing a thin film transistor, the method comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode, the gate insulating layer comprising silicon nitride;

forming a semiconductor layer over the gate insulating layer by using a mixed gas comprising a semiconductor material gas and a nitrogen-containing gas, wherein a concentration of the nitrogen-containing gas is reduced as the formation of the semiconductor layer proceeds;

forming source and drain regions over the semiconductor layer wherein the source and drain regions comprise a semiconductor and an impurity imparting one conductivity type to the semiconductor; and

forming source and drain electrodes over the source and drain regions, respectively.

21. The method according to claim 20,

wherein the nitrogen-containing gas is selected from a nitrogen gas and an ammonia gas.

22. The method according to claim 20,

wherein the mixed gas further comprises a diluent gas.

23. The method according to claim 20,

wherein the mixed gas further comprises a hydrogen gas.

24. The method according to claim 20,

wherein the semiconductor material gas is selected from a silicon hydride gas, a silicon fluoride gas, and a silicon chloride gas.

25. The method according to claim 20,

wherein the gate insulating layer has a stacked structure in which a silicon oxynitride layer is stacked over a silicon nitride layer.

26. The method according to claim 20, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride, and

wherein the exposure of the gate insulating layer to plasma is performed after forming the second gate insulating layer.

27. The method according to claim 20, further comprising a step of forming a second gate insulating layer over and in contact with the gate insulating layer,

wherein the second gate insulating layer comprises silicon oxynitride and has a thickness greater than or equal to 1 nm and less than or equal to 3 nm.