Forming integrated circuits with replacement metal gate electrodes

• US 8,119,508 B2
• Filed: 05/17/2010
• Issued: 02/21/2012
• Est. Priority Date: 08/25/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack, Brask, Justin K., Doczy, Mark L., Metz, Matthew V., Datta, Suman, Shah, Uday, Chau, Robert S.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Reames, Matthew
• Application Number:
  US12/781,084
• Publication Number:
  US 20100219456A1
• Time in Patent Office: 645 Days
• Field of Search: 438/584, 438/595, 257/E21.19, 257/E21.159
• US Class Current: 438/584
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Claims

1. A method comprising:

forming an upper and lower stacked layers and said layers abutting against and surrounded by sidewall spacers;

selectively removing only a portion of each of said spacers around said stacked layers;

covering said stacked layers with material and planarizing said material;

etching said upper layer and stopping the etch on said lower layer;

removing the lower layer to form a trench; and

forming a replacement metal gate in said trench.

2. The method of claim 1, wherein forming said upper and lower stacked layers comprises forming a multi-layer stack of different materials.

3. The method of claim 1, further comprising forming an etch stop layer separating said upper and lower stacked layers.

4. The method of claim 1, further comprising removing and replacing a dielectric layer from a bottom of said trench.

5. The method of claim 1, wherein forming a replacement metal gate in said trench comprises depositing a first metal to only partly fill said trench and filling said trench with a second metal.