Three-dimensional memory structures having shared pillar memory cells

• US 8,120,068 B2
• Filed: 12/24/2008
• Issued: 02/21/2012
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E, Harari, Eliyahou
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): KUO, WENSING W
• Application Number:
  US12/344,022
• Publication Number:
  US 20100155784A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257/211, 257/E25.012, 257/E25.013, 257/E27.026
• US Class Current: 257/211
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Claims

1. A non-volatile memory, comprising:

a first set of array lines elongated in a first direction;

a second set of array lines elongated in a second direction substantially orthogonal to the first direction, the second set of array lines being vertically separated from the first set of array lines; and

a set of pillars in communication with the first set of array lines and the second set of array lines, each pillar of the set of pillars including a first end surface and a second end surface, the first end surface connecting to one array line of the first set of array lines, the second end surface having a first portion connecting to one array line of the second set of array lines and a second portion connecting to a different array line of the second set of array lines, said each pillar including a first non-volatile storage element having a state change element and a steering element and a second non-volatile storage element having a state change element and a steering element, the first portion of the second end surface of said each pillar having a dimension in the first direction that is less than a dimension of the array lines of the second set in the first direction, the second portion of the second end surface of said each pillar having a dimension in the first direction that is less than the dimension of the array lines of the second set in the first direction.

2. A non-volatile memory according to claim 1, wherein:

the first set of array lines is used to sense a data state of the first non-volatile storage element and the second non-volatile storage element in each pillar of the set of pillars.

3. A non-volatile memory according to claim 1, wherein:

the set of pillars includes a first pillar;

the first end surface of the first pillar connects to a first array line of the first set of array lines;

the first portion of the second end surface of the first pillar connects to a second array line of the second set of array lines and a the second portion of the second end surface of the first pillar connects to a third array line of the second set of array lines;

the first non-volatile storage element of the first pillar is addressable by the first array line and the second array line; and

the second non-volatile storage element of the first pillar is addressable by the first array line and the third array line.

4. A non-volatile memory according to claim 3, wherein:

the first pillar includes a first electrode, a second electrode, a third electrode, a first intrinsic region, a first state change element and a second state change element;

the first non-volatile storage element of the first pillar includes the first state change element and a first diode, the first diode formed from the first electrode, the second electrode and the first intrinsic region; and

the second non-volatile storage element of the first pillar includes the second state change element and a second diode, the second diode formed from the first electrode, the third electrode and the first intrinsic region.

5. A non-volatile memory according to claim 4, wherein:

the first pillar includes a dielectric material separating the second electrode from the third electrode and separating the first state change element from the second state change element;

the second electrode and the third electrode are formed from a common layer of conductive material formed at a first height above a substrate; and

the first state change element and the second state change element are formed from a common layer of state change material formed at a second height above the substrate.

6. A non-volatile memory according to claim 4, wherein:

the first intrinsic region is lightly doped.

7. A non-volatile memory according to claim 1, wherein:

the first state change element and the second state change element are antifuses.

8. A non-volatile memory according to claim 1, wherein:

the first state change element and the second state change element are re-writable resistance state change elements.

9. A non-volatile memory according to claim 1, wherein:

the first set of array lines, the second set of array lines and the set of pillars are part of a monolithic three-dimensional memory array including at least two memory levels.

25. A non-volatile memory according to claim 1, wherein:

each pillar includes a first subset of layers that are divided along the first direction; and

each pillar includes a second subset of layers that is shared between the corresponding first non-volatile storage element and second non-volatile storage element.

26. A non-volatile memory according to claim 25, wherein:

the first subset of layers in each pillar includes a first intrinsic layer divided along the first direction; and

the second subset of layers in each pillar includes a second intrinsic region.

27. A non-volatile memory according to claim 25, wherein:

the second end surface of each pillar connects to exactly two array lines of the second set of array lines.

10. A non-volatile memory, comprising:

a first conductor;

a second conductor vertically-separated from the first conductor;

a third conductor vertically-separated from the first conductor, the third conductor being substantially parallel to the second conductor;

a pillar including a first non-volatile storage element and a second non-volatile storage element, the pillar having a first end surface and a second end surface, the first end surface being in contact with the first conductor, the second end surface having a first portion in contact with the second conductor and a second portion in contact with the third conductor;

a first non-volatile storage element formed in the pillar, the first non-volatile storage element including a first diode and a first state change element, the first diode having a first electrode terminating at the first end surface of the pillar and a second electrode separated from the first electrode by a first semiconductor region, the first electrode having a dimension in a first direction that is less than a dimension of the first conductor in the first direction; and

a second non-volatile storage element formed in the pillar, the second non-volatile storage element including a second diode and a second state change element, the second diode sharing the first electrode with the first diode and having a third electrode separated from the first electrode by the first semiconductor region.

11. A non-volatile memory according to claim 10, wherein:

the second electrode of the first diode is separated from the first electrode by the first semiconductor region and a second semiconductor region; and

the third electrode of the second diode is separated from the first electrode by the first semiconductor region and a third semiconductor region.

12. A non-volatile memory according to claim 11, wherein:

the first state change element terminates at the first portion of the second end surface and contacts the second electrode; and

the second state change element terminates at the second portion of the second end surface and contacts the third electrode.

13. A non-volatile memory according to claim 12, wherein:

the first state change element contacts the second semiconductor region and the second electrode, the second electrode terminating at the first portion of the second end surface; and

the second state change element contacts the third semiconductor region and the third electrode, the third electrode terminating at the second portion of the second end surface.

14. A non-volatile memory according to claim 10, wherein:

the pillar includes a dielectric material separating the second electrode from the first electrode; and

the dielectric material separates the first state change element from the second state change element.

28. A non-volatile memory according to claim 10, wherein:

each pillar includes a first subset of layers that are divided along the first direction; and

each pillar includes a second subset of layers that is shared between the corresponding first non-volatile storage element and second non-volatile storage element.

29. A non-volatile memory according to claim 11, wherein:

the first semiconductor region is a first intrinsic region;

the second semiconductor region is a second intrinsic region; and

the third semiconductor region is a third intrinsic region.

15. A non-volatile memory, comprising:

a first set of conductors elongated in a first direction;

a second set of conductors elongated in a second direction substantially orthogonal to the first direction, the second set of conductors vertically separated from the first set of conductors;

a first pillar having a first end surface in contact with a first conductor of the first set of conductors and a second end surface in contact with a first conductor of the second set of conductors and a second conductor of the second set of conductors;

a first diode formed in the first pillar having a first electrode terminating at the first end surface and a second electrode separated from the first electrode by at least a first semiconductor region;

a second diode formed in the first pillar sharing the first electrode with the first diode and having a third electrode separated from the first electrode by at least the first semiconductor region;

a second pillar adjacent to the first pillar in the second direction, the second pillar having a first end surface in contact with a second conductor of the first set of conductors, the second pillar having a second end surface in contact with the first conductor of the second set of conductors and the second conductor of the second set of conductors;

a third diode formed in the second pillar having a fourth electrode terminating at the first end surface of the second pillar and a fifth electrode separated from the fourth electrode by at least a second semiconductor region, the fourth electrode of the second pillar being physically separate from the first electrode of the first pillar; and

a fourth diode formed in the second pillar sharing the fourth electrode with the third diode and having a sixth electrode separated from the fourth electrode by at least the second semiconductor region.

16. A non-volatile memory according to claim 15, wherein:

the first pillar has a length in the first direction and a width in the second direction; and

the length in the first direction is more than twice the width in the second direction.

17. A non-volatile memory, comprising:

a first set of conductors elongated in a first direction;

a second set of conductors elongated in a second direction substantially orthogonal to the first direction, the second set of conductors vertically separated from the first set of conductors;

a first pillar having a first end surface in contact with a first conductor of the first set of conductors and a second end surface in contact with a first conductor of the second set of conductors and a second conductor of the second set of conductors;

a first diode formed in the first pillar having a first electrode terminating at the first end surface and a second electrode separated from the first electrode by at least a first semiconductor region;

a second diode formed in the first pillar sharing the first electrode with the first diode and having a third electrode separated from the first electrode by at least the first semiconductor region;

a second pillar having a first end surface in contact with a second conductor of the first set of conductors, the second pillar having a second end surface in contact with the second conductor of the second set of conductors and a third conductor of the second set of conductors, the second end surface is not in contact with the first conductor of the second set of conductors;

a third diode formed in the second pillar having a fourth electrode terminating at the first end surface of the second pillar and a fifth electrode separated from the fourth electrode by at least a second semiconductor region, the fourth electrode of the second pillar being physically separate from the first electrode of the first pillar; and

a fourth diode formed in the second pillar sharing the fourth electrode with the third diode and having a sixth electrode separated from the fourth electrode by at least the second semiconductor region.

18. A non-volatile memory according to claim 17, wherein:

the first and second pillars are part of a set of pillars in communication with the first set of conductor and the second set of conductors;

the first set of conductor and the second set of conductor cross at a number of locations; and

a number of pillars in the set of pillars is substantially less than the number of locations at which the first set of conductors and the second set of conductors cross.

19. A non-volatile memory according to claim 18, wherein:

the number of pillars in the set is substantially half of the number of locations at which the first set of conductors and the second set of conductors cross.

20. A non-volatile memory, comprising:

a first set of conductors elongated in a first direction;

a second set of conductors elongated in a second direction substantially orthogonal to the first direction, the second set of conductors vertically separated from the first set of conductors;

a first pillar having a first end surface in contact with a first conductor of the first set of conductors and a second end surface in contact with a first conductor of the second set of conductors and a second conductor of the second set of conductors;

a first diode formed in the first pillar having a first electrode terminating at the first end surface and a second electrode separated from the first electrode by at least a first semiconductor region;

a second diode formed in the first pillar sharing the first electrode with the first diode and having a third electrode separated from the first electrode by at least the first semiconductor region;

a second pillar adjacent to the first pillar in the first direction, the second pillar having a first end surface in contact with the first conductor and a second end surface in contact with a third conductor of the second set of conductors and a fourth conductor of the second set of conductors;

a third diode formed in the second pillar having a fourth electrode terminating at the first end surface of the second pillar and a fifth electrode separated from the fourth electrode by at least a second semiconductor region, the fourth electrode of the second pillar being physically separate from the first electrode of the first pillar; and

a fourth diode formed in the second pillar sharing the fourth electrode with the third diode and having a sixth electrode separated from the fourth electrode by at least the second semiconductor region.

21. A non-volatile memory according to claim 20, wherein:

there is no pillar having a first end surface in contact with the first conductor of the first set of conductors and a second end surface in contact with the second conductor of the second set of conductors and the third conductor of the second set of conductors.

22. A non-volatile memory, comprising:

a first array line elongated in a first direction over a substrate;

a second array line elongated in a second direction over the substrate and vertically separated from the first array line, the second direction being substantially orthogonal to the first direction;

a third array line elongated in the second direction over the substrate and vertically separated from the first array line, the second array line and the third array line being substantially coplanar and substantially parallel array lines;

a pillar having a first end surface in contact with the first array line and a second end surface with a first portion in contact with the second array line and a second portion in contact with the third array line;

a first state change element formed in the pillar and terminating at the first portion of the second end surface;

a second state change element formed in the pillar and terminating at the second portion of the second end surface, the first state change element and the second state change element being separated in the first direction by a dielectric material;

a first diode in series with the first state change element, the first diode having a first electrode terminating at the first end surface of the pillar and a second electrode separated from the first electrode by a first intrinsic region and a second intrinsic region; and

a second diode in series with the second state change element, the second diode sharing the first electrode with the first diode and having a third electrode separated from the first electrode by the first intrinsic region and a third intrinsic region, the second electrode and the third electrode being separated in the first direction by the dielectric material.

23. A non-volatile memory according to claim 22, wherein:

the first state change element and the second state change element are formed from a commonly deposited layer of state change material; and

the second electrode and the third electrode are formed from a commonly deposited layer of state change material.

24. A non-volatile memory according to claim 23, wherein:

a sum of a width in the first direction of the second electrode, the third electrode and the dielectric material is equal to a width in the first direction of the first electrode;

the width of the first electrode in the first direction is equal to a width of the pillar in the first direction.