Non-volatile memory cell and array

• US 8,120,088 B1
• Filed: 04/18/2008
• Issued: 02/21/2012
• Est. Priority Date: 12/07/2007
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: She, Min, Wang, Chih-Hsin
• Primary Examiner(s): Wright, Tucker
• Application Number:
  US12/105,988
• Time in Patent Office: 1,404 Days
• Field of Search: 257314-326, 257/E29.129, 257/E29.3, 257/E21.68
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×10¹⁹ atoms/cm³.

Claims

1. A semiconductor memory cell array comprising a plurality of memory cells, each memory cell including:

a first element, a second element and a channel between the first element and the second element in a body, a charge storage region juxtaposed the channel, the first element and the second element extending in a first direction through the plurality of memory cells;

an element conductor juxtaposed the first element and extending in the first direction through the plurality of memory cells continuously coupling to the first element;

a line conductor juxtaposed the charge storage region and extending in a second direction normal to the first direction; and

a line insulator for insulating the element conductor from the line conductor.

2. The semiconductor memory cell array of claim 1, wherein the charge storage region comprises polysilicon.

3. The semiconductor memory cell array of claim 1, wherein the charge storage region has a height in a range from approximately 10 nanometers to approximately 120 nanometers.

4. The semiconductor memory cell array of claim 1, wherein the charge storage region comprises a plurality of spaced-apart nanoparticles.

5. The semiconductor memory cell array of claim 4, wherein the nanoparticles comprise material selected from the group consisting of Si, Ge, HfO₂, Au, Ag, Pt, combinations thereof, and alloys thereof.

6. The semiconductor memory cell array of claim 4, wherein the nanoparticles include nanoparticles having diameters in a range from approximately 5 nanometers to approximately 20 nanometers.

7. The semiconductor memory cell array of claim 1, wherein the charge storage region comprises a dielectric having a plurality of trapping centers.

8. The semiconductor memory cell array of claim 7, wherein the dielectric comprises material selected from the group consisting of silicon nitride (SiN), hafnium oxide (HfO₂), oxynitride, combinations thereof, and alloys thereof.

9. The semiconductor memory cell array of claim 1, each memory cell further including:

a channel insulator between the channel and the charge storage region.

10. The semiconductor memory cell array of claim 1, each memory cell further including:

an element conductor insulator between the element conductor and the charge storage region.

11. The semiconductor memory cell array of claim 1, each memory cell further including:

a line conductor insulator between the line conductor and the charge storage region.

12. The semiconductor memory cell array of claim 1, each memory cell further including:

a first insulator between the channel and the charge storage region;

a second insulator between the element conductor and the charge storage region; and

a third insulator between the line conductor and the charge storage region.

13. The semiconductor memory cell array of claim 12, wherein two or more of the first insulator, the second insulator, and the third insulator are formed of the same material.

14. The semiconductor memory cell array of claim 12, wherein one or more of the first insulator, the second insulator, and the third insulator are formed of one or more layers of insulating material.

15. The semiconductor memory cell array of claim 12, wherein one or more of the first insulator, the second insulator, and the third insulator are formed of one or more layers of material selected from the group consisting of oxide, nitride, oxynitride, combinations thereof, and alloys thereof.

16. The semiconductor memory cell array of claim 12, wherein the first insulator, the second insulator, and the third insulator are each formed of one or more layers of materials haying a thickness in a range from approximately 1 nanometer to approximately 20 nanometers.

17. The semiconductor memory array of claim 1, wherein the line insulator has a thickness in a range from approximately 5 nanometers to approximately 50 nanometers.

18. The semiconductor memory array of claim 1, wherein the element conductor has a thickness in a range from approximately 20 to approximately 200 nanometers.

19. The semiconductor memory cell array of claim 1, wherein the element conductor is a semiconductor having a doping level in a range from approximately 1×

10¹⁹ atoms/cm³ to approximately 1×

10²¹ atoms/cm³.

20. The semiconductor memory cell array of claim 1, wherein the element conductor has a sheet resistance in a range from approximately 1 ohm/square to approximately 200 ohms/square.

21. The semiconductor memory cell array of claim 1, wherein the element conductor is a material selected from the group consisting of polysilicon, amorphous silicon, polysilicon germanium, amorphous silicon germanium, metal, combinations thereof, and alloys thereof.

22. The semiconductor memory cell array of claim 1, wherein a length of the channel is less than about 130 nanometers.

23. The semiconductor memory cell array of claim 1, wherein the first element and the second element are semiconductor elements having doping levels in a range from approximately 5×

10¹⁸ atoms/cm³ to approximately 5×

10¹⁹ atoms/cm³.

24. The semiconductor memory cell array of claim 1, wherein the first element and the second element have depths into the body in a range from approximately 5 nanometers to approximately 200 nanometers.

25. The semiconductor memory cell array of claim 1, wherein the first element and the second element have sheet resistances of greater than approximately 80 ohms/square.

26. The semiconductor memory cell array of claim 1, wherein a conductivity of the first element is substantially less than the conductivity of the element conductor whereby a first combined conductivity of the first element and the element conductor is substantially greater than the conductivity of the first element.

27. The semiconductor memory cell array of claim 1, each memory cell further including:

a tunneling gate in proximity to the line conductor and juxtaposed the charge storage region; and

a gate insulator between the tunneling gate and the line conductor.

28. The semiconductor memory cell array of claim 27, wherein the gate insulator is a filter.

29. The semiconductor memory cell array of claim 28, wherein the filter includes multiple layers, each layer comprising material selected from the group consisting of oxide, nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, combinations thereof, and alloys thereof.

30. The semiconductor memory cell array of claim 28, wherein the filter includes a first layer formed of oxide and a second layer formed of material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, combinations thereof, and alloys thereof.

31. The semiconductor memory cell array of claim 28, wherein the filter includes a first layer formed of oxynitride and a second layer formed, of material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, combinations thereof and alloys thereof.

32. A memory array including a plurality of memory cells extending in a first direction and in a second direction,

each memory cell including:

a first element, a second element and a channel between the first element and the second element in a body;

a charge storage region juxtaposed the channel;

a first element conductor and a second element conductor in contact with the first element and the second element, respectively;

a line conductor juxtaposed the charge storage region; and

line insulators for insulating the element conductors from the line conductors,

wherein the line conductor extends to a first plurality of the memory cells in the first direction so as to be juxtaposed the charge storage regions in each of the plurality of memory cells; and

wherein the first element and the second element, and the first element conductor and the second element conductor, from one memory cell extend to another memory cell, whereby the first element and the first element conductor, and the second element and the second element conductor, respectively, are in contact in the plurality of memory cells.

33. The memory array of claim 32, wherein:

a conductivity of the first element is substantially less than a conductivity of the first element conductor whereby a combined conductivity of the first element and the first element conductor is substantially greater than the conductivity of the first element; and

a conductivity of the second element is substantially less than a conductivity of the second element conductor whereby a combined conductivity of the second element and the second element conductor is substantially greater than the conductivity of the second element.

34. The memory array of claim 32, each memory cell further including:

a tunneling gate in proximity to the line conductor and juxtaposed the charge storage region; and

a gate insulator between the tunneling gate and the line conductor.

35. The memory array of claim 34, wherein the gate insulator is a filter.

36. The memory array of claim 35, wherein the filter includes multiple layers, each layer comprising material selected from the group consisting of oxide, nitride oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, combinations thereof, and alloys thereof.