Semiconductor device and method of forming the same

• US 8,120,123 B2
• Filed: 04/01/2010
• Issued: 02/21/2012
• Est. Priority Date: 09/18/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoshida, Makoto, Hong, Hyeong-Sun, Yeom, Kye-Hee, Kim, Dae-Ik, Kim, Yong-Il
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US12/662,150
• Publication Number:
  US 20100193880A1
• Time in Patent Office: 691 Days
• Field of Search: 257/401, 257/773, 257/E27.06, 257/E23.141
• US Class Current: 257/401
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

Claims

1. A semiconductor device, comprising:

an inactive region configured to define first and second active regions in a semiconductor substrate;

a first upper interconnection disposed on the inactive region adjacent to the first active region;

a first contact plug configured to have a top surface at a same level as a top surface of the first upper interconnection and contact the first active region and the first upper interconnection;

a second lower interconnection configured to have a top surface disposed at the same level as the top surface of the first contact plug and disposed on the second active region;

a second upper interconnection disposed on the second lower interconnection; and

a second contact plug configured to contact the second upper interconnection and the second active region.

2. The device as claimed in claim 1, wherein the first and second upper interconnections have different structures and include bit lines.

3. The device as claimed in claim 2, further comprising a first lower interconnection configured to intersect the second upper interconnection,

wherein the first lower interconnection protrudes upward from a top surface of the semiconductor substrate and extends downward from the top surface of the semiconductor substrate.

4. The device as claimed in claim 3, wherein:

the first and second lower interconnections have different structures and include gates,

the first lower interconnection has a top surface that is substantially planar across the first active region and the inactive region or has a higher top surface in the inactive region than in the first active region, and

the second lower interconnection is formed of the same material as the first upper interconnection.

5. The device as claimed in claim 4, wherein the first lower and upper interconnections electrically interact with each other through the first active region and the first contact plug, and the second lower and upper interconnections electrically interact with each other through the second active region and the second contact plug.

6. The device as claimed in claim 5, wherein the first and second contact plugs have the same structure and the second contact plug has a top surface at the same level as the top surface of the second lower interconnection.

7. The device as claimed in claim 5, wherein a first end of the first contact plug is inserted into an upper portion of the first upper interconnection, and a second end of the first contact plug contacts the first active region and the inactive region disposed adjacent to the first active region.

8. The device as claimed in claim 7, further comprising first and second gate spacers sequentially stacked on each of both sidewal Is of the second lower interconnection.

9. The device as claimed in claim 8, wherein the first upper interconnection is disposed parallel to the first active region and at a right angle to the first lower interconnection.

10. The device as claimed in claim 8, wherein the first upper interconnection is disposed parallel to the first active region and oblique to the first lower interconnection.

11. A semiconductor device, comprising:

inactive regions disposed in a cell array region and a peripheral circuit region of a semiconductor substrate;

cell and peripheral active regions defined by the inactive regions in the cell array region and the peripheral circuit region;

a first interconnection, a second interconnection, and a cell contact plug disposed in the cell array region, wherein the first interconnection is disposed on the cell active region and the inactive region disposed adjacent to the cell active region, the second interconnection is disposed on the inactive region adjacent to the cell active region and configured to intersect the first interconnection, and the cell contact plug is configured to have a top surface at substantially a same level as a top surface of the second interconnection and contacts the cell active region and the second interconnection; and

a third interconnection, a fourth interconnection, and a peripheral contact plug disposed in the peripheral circuit region, wherein the third interconnection is disposed on the peripheral active region, formed of the same material as the second interconnection, and configured to have a top surface at the same level as the top surface of the cell contact plug, the fourth interconnection is disposed on the third interconnection, and the peripheral contact plug is configured to contact the peripheral active region and the fourth interconnection,

wherein the first interconnection is partially inserted into the second interconnection across the second interconnection or contacts the second interconnection under the second interconnection across the second interconnection.

12. The device as claimed in claim 11, wherein the first and third interconnections are disposed at different levels on the semiconductor substrate and have gates with different structures, the second and fourth interconnections are disposed at different levels on the semiconductor substrate and have bit lines with different structures, and the second and third interconnections are formed of the same material.

13. The device as claimed in claim 12, wherein the cell and peripheral contact plugs have the same structure and the peripheral contact plug has a top surface at the same level as the top surface of the third interconnection.

14. The device as claimed in claim 12, wherein the second interconnection is disposed parallel to the cell active region and at a right angle to the first interconnection.

15. The device as claimed in claim 12, wherein the second interconnection includes two lines defining an inflection point, the cell active region is disposed parallel to the respective two lines of the second interconnection, and the first interconnection is disposed oblique to the cell active region and the second interconnection.

16. The device as claimed in claim 12, wherein the second interconnection includes two lines defining an inflection point, the cell active region has a center corresponding to the inflection point between the two lines of the second interconnection and is disposed parallel to the two lines of the second interconnection, and the first interconnection is disposed oblique to the cell active region and the second interconnection.