Post passivation interconnection process and structures

• US 8,120,181 B2
• Filed: 07/30/2008
• Issued: 02/21/2012
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chiu-Ming, Chou, Chien-Kang
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US12/182,148
• Publication Number:
  US 20080290520A1
• Time in Patent Office: 1,301 Days
• Field of Search: 257/758, 257/760, 257762-764, 257/766, 257/779, 257/781, 257/E23.142, 257/E23.161
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. An integrated circuit comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a separating layer over said first metallization structure and said dielectric layer, wherein said separating layer comprises a nitride, wherein a first opening in said separating layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening;

a first polymer layer over said separating layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a second metallization structure on said first polymer layer, wherein said second metallization structure is connected to said first contact point through said first opening and a second opening in said first polymer layer, wherein said second metallization structure comprises a glue layer and an electroplated copper layer over said glue layer, wherein an undercut has an edge of said glue layer recessed from an edge of said electroplated copper layer; and

a second polymer layer on said second metallization structure.

2. The integrated circuit of claim 1, wherein said first polymer layer comprises polyimide.

3. The integrated circuit of claim 1, wherein said second metallization structure further comprises a copper seed layer between said glue layer and said electroplated copper layer.

4. The integrated circuit of claim 1, wherein said glue layer comprises titanium.

5. The integrated circuit of claim 1, wherein said glue layer comprises titanium nitride.

6. The integrated circuit of claim 1, wherein said glue layer comprises a titanium-tungsten alloy.

7. The integrated circuit of claim 1, wherein a third opening in said separating layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said third opening, wherein said second metallization structure is connected to said second contact point through said third opening and a fourth opening in said first polymer layer, wherein said first contact point is connected to said second contact point through said second metallization structure.

8. The integrated circuit of claim 1, wherein said second metallization structure further comprises a nickel layer on said electroplated copper layer.

9. The integrated circuit of claim 8, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.

10. The integrated circuit of claim 1, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.