Voltage controlled oscillator delay cell and method

• US 8,120,408 B1
• Filed: 07/14/2008
• Issued: 02/21/2012
• Est. Priority Date: 05/05/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sivadasan, Mohandas Palatholmana, Rohilla, Gajendar
• Primary Examiner(s): Luu, An T
• Application Number:
  US12/218,404
• Time in Patent Office: 1,317 Days
• Field of Search: 327/261, 327/263, 327/265, 327/285, 327/287, 327/288, 327/52, 327/55
• US Class Current: 327/261
• CPC Class Codes: H03H 11/265 with adjustable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

Claims

1. A delay cell circuit, comprising:

a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, the differential stage including a first variable current source that provides a differential stage current that decreases in response to a first control input; and

a cross-coupled stage coupled to the differential output terminals and including a first gain attenuating resistor and a second variable current source, coupled to commonly coupled second terminals of the first and a second gain attenuating resistor, that provides a cross-coupled stage current that increases in response to the control input.

2. The delay cell circuit of claim 1, wherein

the cross-coupled stage includes the second gain attenuating resistor.

3. The delay cell circuit of claim 2, wherein:

the cross-coupled stage includes

a first transistor having a gate coupled to the first differential output terminal, a drain coupled to the second differential output terminal, and a source coupled to a first terminal of the first gain attenuating resistor; and

a second transistor having a gate coupled to the second differential output terminal, a drain coupled to the first differential output terminal, and a source coupled to a first terminal of the second gain attenuating resistor.

4. The delay cell circuit of claim 1, wherein:

the differential stage includes

a first differential transistor having a gate coupled to the first differential input terminal, a drain coupled to the first differential output terminal, and a source;

a second differential transistor having a gate coupled to the second differential input terminal, a drain coupled to the second differential output terminal, and a source commonly coupled to the source of the first differential transistor; and

the second variable current source is coupled to the commonly coupled sources of the first and second differential transistors.

5. The delay cell circuit of claim 4, wherein:

the second variable current source includes a second constant current source component coupled between the commonly coupled sources of the first and second differential transistors and a first reference voltage and a second variable current source component coupled between the commonly coupled sources of the first and second differential transistors and a second reference voltage and the second variable current source component varies in accordance with the control input, which comprises a control voltage.

6. The delay cell circuit of claim 5, wherein:

the delay cell circuit comprises a portion of a voltage control oscillator and the second variable current source component decreases current as frequency of oscillation increases.

7. A delay cell circuit, comprising:

a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, and including a first voltage controlled variable current source that varies a differential stage current in a first way in response to a control voltage; and

a cross-coupled stage coupled to the differential output terminals and including a first gain attenuating resistor, and a second voltage controlled variable current source coupled to commonly coupled second terminals of the first and a second gain attenuating resistor that varies a cross-coupled stage current in a second way, different from the first way, in response to the control voltage.

8. The delay cell circuit of claim 7, wherein:

the delay cell circuit comprises a portion of a voltage controlled oscillator and the first voltage controlled variable current source provides a current to the first gain attenuating resistor that decreases as the frequency increases.

9. The delay cell circuit of claim 7, wherein:

the delay cell circuit comprises a portion of a voltage controlled oscillator and the voltage controlled variable current source provides a current to the differential stage that increases as the frequency increases.

10. A delay cell circuit, comprising:

a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, and including a voltage controlled variable current source providing current for the differential stage; and

a cross-coupled stage coupled to the differential output terminals comprising a gain attenuating circuit and a first cross-coupled stage including a first transistor with a drain directly connected to the first differential output terminal and a gate directly connected to the second differential output terminal, and a second transistor with a drain directly connected to the second differential output terminal and a gate directly connected to the first differential output terminal.

11. The delay cell circuit of claim 10, wherein:

the cross-coupled stage includes

a first voltage controlled variable current source providing current for the cross-coupled stage.

12. The delay cell circuit of claim 11, wherein:

the delay cell circuit comprises a portion of a voltage controlled oscillator and the first voltage controlled variable current source provides a current to the cross-coupled stage that decreases as the frequency increases.

13. The delay cell circuit of claim 10, wherein:

the delay cell circuit comprises a portion of a voltage controlled oscillator and the voltage controlled variable current source provides a current to the differential stage that increases as the frequency increases.

14. The delay cell circuit of claim 10 further including:

the first and second differential output terminals are each coupled to a resistor/capacitor circuit; and

the gain attenuating circuit includes a pair of essentially matching resistors having a resistance value in the range of about 75-150 ohms coupled between common sources of a first and second cross-coupled transistors, the first cross-coupled transistor having a drain coupled to the first differential output node and the second cross-coupled transistor having a drain coupled to the second differential output node.