Voltage controlled oscillator delay cell and method
First Claim
1. A delay cell circuit, comprising:
- a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, the differential stage including a first variable current source that provides a differential stage current that decreases in response to a first control input; and
a cross-coupled stage coupled to the differential output terminals and including a first gain attenuating resistor and a second variable current source, coupled to commonly coupled second terminals of the first and a second gain attenuating resistor, that provides a cross-coupled stage current that increases in response to the control input.
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Accused Products
Abstract
A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.
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Citations
14 Claims
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1. A delay cell circuit, comprising:
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a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, the differential stage including a first variable current source that provides a differential stage current that decreases in response to a first control input; and a cross-coupled stage coupled to the differential output terminals and including a first gain attenuating resistor and a second variable current source, coupled to commonly coupled second terminals of the first and a second gain attenuating resistor, that provides a cross-coupled stage current that increases in response to the control input. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A delay cell circuit, comprising:
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a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, and including a first voltage controlled variable current source that varies a differential stage current in a first way in response to a control voltage; and a cross-coupled stage coupled to the differential output terminals and including a first gain attenuating resistor, and a second voltage controlled variable current source coupled to commonly coupled second terminals of the first and a second gain attenuating resistor that varies a cross-coupled stage current in a second way, different from the first way, in response to the control voltage. - View Dependent Claims (8, 9)
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10. A delay cell circuit, comprising:
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a differential stage coupled to receive a differential input voltage at first and second differential input terminals and provide a differential output voltage at first and second differential output terminals, and including a voltage controlled variable current source providing current for the differential stage; and a cross-coupled stage coupled to the differential output terminals comprising a gain attenuating circuit and a first cross-coupled stage including a first transistor with a drain directly connected to the first differential output terminal and a gate directly connected to the second differential output terminal, and a second transistor with a drain directly connected to the second differential output terminal and a gate directly connected to the first differential output terminal. - View Dependent Claims (11, 12, 13, 14)
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Specification