Stable VCO operation in absence of clock signal
First Claim
1. A semiconductor device having a phase-locked loop (“
- PLL”
), comprising;
a voltage-controlled oscillator (“
VCO”
) configured to generate an output clock signal having an output frequency controlled by a control voltage;
a charge pump configured to output current pulses in response to a plurality of UP control pulses and a plurality of DOWN control pulses;
a loop filter configured to generate the control voltage in response to the current pulses from the charge pump;
a phase-frequency detector (“
PFD”
) wherein;
in response to a reference frequency of a first reference clock signal being present at the PFD and the output frequency of the output clock signal being locked to the reference frequency, the PFD generates the UP and DOWN control pulses to maintain the control voltage in a locked condition of the PLL, wherein one or more of the UP control pulses are simultaneous with one or more of the DOWN control pulses, respectively, andin response to the reference frequency of the first reference clock signal not being present at the PFD, the PFD generates the UP control pulses alternating with the DOWN control pulses based on a second reference clock signal.
1 Assignment
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Accused Products
Abstract
A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.
23 Citations
20 Claims
-
1. A semiconductor device having a phase-locked loop (“
- PLL”
), comprising;a voltage-controlled oscillator (“
VCO”
) configured to generate an output clock signal having an output frequency controlled by a control voltage;a charge pump configured to output current pulses in response to a plurality of UP control pulses and a plurality of DOWN control pulses; a loop filter configured to generate the control voltage in response to the current pulses from the charge pump; a phase-frequency detector (“
PFD”
) wherein;in response to a reference frequency of a first reference clock signal being present at the PFD and the output frequency of the output clock signal being locked to the reference frequency, the PFD generates the UP and DOWN control pulses to maintain the control voltage in a locked condition of the PLL, wherein one or more of the UP control pulses are simultaneous with one or more of the DOWN control pulses, respectively, and in response to the reference frequency of the first reference clock signal not being present at the PFD, the PFD generates the UP control pulses alternating with the DOWN control pulses based on a second reference clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
- PLL”
-
8. A semiconductor device having a phase-locked loop (“
- PLL”
), comprising;a voltage-controlled oscillator (“
VCO”
) generating an output clock signal having an output frequency controlled by a control voltage;a charge pump configured to output current pulses in response to a plurality of UP control pulses and a plurality of DOWN control pulses; a loop filter producing the control voltage controlling the VCO in response to the current pulses from the charge pump; a phase-frequency detector (“
PFD”
) for locking the output frequency of the output clock signal to a reference clock frequency of a first reference clock signal in response to the first reference clock signal being present at the PFD;a voltage generator producing a generated voltage at an intermediate node, the voltage generator including at least one CMOS leg disposed between a first reference voltage and a second reference voltage, each CMOS leg including a PMOS device in series with an NMOS device and having an intermediate node between the PMOS device and the NMOS device; a comparator comparing the generated voltage to the control voltage to produce adjustment pulses when the generated voltage does not equal the control voltage; a counter counting the adjustment pulses to produce adjustment bits; and a decoder circuit producing a PMOS adjustment signal and an NMOS adjustment signal coupled to the voltage generator according to the adjustment bits to adjust the generated voltage closer to the control voltage, wherein the PMOS adjustment signal adjusts a first channel resistance of the PMOS device in each CMOS leg and the NMOS adjustment signal adjusts a second channel resistance of the NMOS device in each CMOS leg, and the generated voltage produced at the intermediate node is a function of the first and second channel resistances through the PMOS and NMOS devices of the at least one CMOS leg. - View Dependent Claims (9, 10, 11, 12, 13)
- PLL”
-
14. A method of operating a phase-locked loop (“
- PLL”
) circuit in an integrated circuit (“
IC”
) comprising;establishing an initial control voltage from a loop filter to a VCO of the PLL circuit with a clock reference signal present at the PLL circuit; generating a generated voltage on the IC from a reference voltage; comparing the generated voltage to the initial control voltage; producing adjustment pulses; adjusting the generated voltage to replicate the initial control voltage by counting the adjustment pulses to produce adjustment bits; decoding the adjustment bits to produce a first adjustment signal biasing a PMOS device of a CMOS leg in a voltage generator circuit to produce a PMOS channel resistance and a second adjustment signal biasing an NMOS device of the CMOS leg to produce an NMOS channel resistance to produce an adjusted generated voltage at an intermediate node of the CMOS leg according to a ratio of the PMOS channel resistance and the NMOS device channel resistance; detecting whether the clock reference signal is present, and, if the clock reference signal is not present; and driving the loop filter with the adjusted generated voltage. - View Dependent Claims (15, 16, 17, 18, 19, 20)
- PLL”
Specification