High voltage word line driver

• US 8,120,968 B2
• Filed: 02/12/2010
• Issued: 02/21/2012
• Est. Priority Date: 02/12/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William Robert, Barth, John Edward Jr., Kirihata, Toshiaki, Leu, Derek H., Plass, Donald W.
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US12/704,703
• Publication Number:
  US 20110199837A1
• Time in Patent Office: 739 Days
• Field of Search: 365/185.23, 365/189.06, 365/189.11, 365/189.07, 365/185.05
• US Class Current: 365/185.23
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

Claims

1. A word line driver circuit adapted for connection to a corresponding word line in a memory circuit, the word line driver circuit comprising:

a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit;

a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal;

a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and

a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;

wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.

2. The word line driver circuit of claim 1, wherein each of the first, second, third and fourth transistors is a thin-oxide MOS transistor.

3. The word line driver circuit of claim 1, wherein each of the first and second transistors is a thin-oxide PMOS transistor, and each of the third and fourth transistors is a thin-oxide NMOS transistor.

4. The word line driver circuit of claim 1, wherein the first voltage level is higher than the second, third and fourth voltage levels, and wherein the second voltage level is lower than the third and fourth voltage levels.

5. The word line driver circuit of claim 1, wherein the fourth voltage level is between the first and third voltage levels.

6. The word line driver circuit of claim 1, wherein the third and fourth voltage levels are about equal to one another.

7. The word line driver circuit of claim 1, wherein the third and fourth voltage levels are equal to approximately one-half of the first voltage level plus one-half of the second voltage level.

8. The word line driver circuit of claim 1, wherein at least one of:

(i) a lower limit of a voltage on the second source/drain of the first transistor is defined by the third voltage level plus a magnitude of a threshold voltage of the second transistor; and

(ii) an upper limit of a voltage on the first source/drain of the fourth transistor is defined by the fourth voltage level minus a magnitude of a threshold voltage of the fourth transistor.

9. The word line driver circuit of claim 2, wherein a magnitude of a difference between a voltage on the gate and a voltage on the first source/drain, and a magnitude of a difference between a voltage on the gate and a voltage on the second source/drain for each of the first, second, third and fourth transistors has an upper limit equal to about one-half of the first voltage level minus one-half of the second voltage level.

10. The word line driver circuit of claim 1, further comprising at least one of:

a first voltage level shifter circuit coupled to the gate of the first transistor, the first voltage level shifter circuit being operative to receive the input signal referenced to a first set of signal levels and to generate the first control signal referenced to a second set of signal levels; and

a second voltage level shifter circuit coupled to the gate of the fourth transistor, the second voltage level shifter circuit being operative to receive the input signal referenced to the first set of signal levels and to generate the second control signal referenced to a third set of signal levels.

11. The word line driver circuit of claim 1, wherein the first voltage level shifter circuit includes a first voltage supply node coupled to the first voltage supply providing the first voltage level and a second voltage supply node coupled to a third voltage supply providing a fifth voltage level, the fifth voltage level being less than the first voltage level, and wherein the second voltage level shifter circuit includes a first voltage supply node coupled to a fourth voltage supply providing a sixth voltage level and a second voltage supply node coupled to the second voltage supply providing the second voltage level, the sixth voltage level being greater than the second voltage level.

12. The word line driver circuit of claim 1, further comprising a switching circuit coupled to the gate of the second transistor, the switching circuit being operative to generate the first clamp signal which switches between the third voltage level and a fifth voltage level as a function of the input signal supplied to the word line driver circuit, the fifth voltage level being less than the third voltage level.

13. The word line driver circuit of claim 12, wherein the word line driver circuit is operative:

(i) to drive the corresponding word line to a first word line voltage level when the first clamp signal is at the third voltage level; and

(ii) to drive the corresponding word line to a second word line voltage level when the first clamp signal is at the fifth voltage level.

14. The word line driver circuit of claim 13, wherein the first word line voltage level is substantially equal to the first voltage level, and the second word line voltage level is substantially equal to the second voltage level.

15. The word line driver circuit of claim 1, wherein at least one of:

the first control signal has a lower limit substantially equal to a magnitude of a threshold voltage of the first transistor above the first clamp signal; and

the second control signal has an upper limit substantially equal to a magnitude of a threshold voltage of the fourth transistor below the second clamp signal.

16. The word line driver circuit of claim 1, further comprising at least one of:

a fifth transistor including a first source/drain connected to the gate of the first transistor, a second source/drain for receiving the first control signal, and a gate for receiving a third clamp signal, a voltage applied to the gate of the first transistor having a lower limit substantially equal to a magnitude of a threshold voltage of the fifth transistor above the third clamp signal; and

a sixth transistor including a first source/drain connected to the gate of the fourth transistor, a second source/drain for receiving the second control signal, and a gate for receiving a fourth clamp signal, the second control signal having an upper limit substantially equal to a magnitude of a threshold voltage of the sixth transistor below the fourth clamp signal.

17. The word line driver circuit of claim 16, wherein the first, second, third and fourth third clamp signals are substantially equal to one another.

18. The word line driver circuit of claim 16, wherein the third clamp signal is substantially equal to the first clamp signal, and wherein the fourth clamp signal is substantially equal to the second clamp signal.

19. The word line driver circuit of claim 16, wherein at least a given one of the first, second, third, fourth, fifth and sixth transistors comprises a thin-oxide MOS transistor adapted to withstand a voltage difference between any two of the first source/drain, second source/drain and gate thereof that is less than a magnitude of a difference between the first and second voltage levels.

20. A memory circuit, comprising:

at least one word line;

at least one memory cell coupled to the at least one word line; and

at least one word line driver circuit coupled to the at least one word line, the at least one word line driver circuit comprising;

a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit;

a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal;

a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and

a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;

wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.

21. An integrated circuit, comprising:

an embedded memory; and

at least one word line driver circuit connected to a corresponding word line in the embedded memory, the at least one word line driver circuit comprising;

a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit;

a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal;

a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and

a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;

wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.

22. The integrated circuit of claim 21, wherein the embedded memory comprises a dynamic random access memory.