Semi-volatile NAND flash memory

• US 8,120,969 B1
• Filed: 08/10/2011
• Issued: 02/21/2012
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Montierth, Mark D., Briggs, Randall D., Keithley, Douglas G.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/207,277
• Time in Patent Office: 195 Days
• Field of Search: 365/185.25
• US Class Current: 365/185.25
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Claims

1. A method comprising:

partitioning a NAND flash memory into a plurality of retention regions, wherein the plurality of retention regions includes a first retention region and a second retention region;

writing data in a first memory block of the first retention region;

determining that the data written in the first memory block needs to be refreshed; and

based on determining that the data written in the first memory block needs to be refreshed,

(i) if the first memory block has endured at least a threshold number of erase/write cycles, relocating the data from the first memory block to a second memory block of the second retention region, and

(ii) if the first memory block has endured less than the threshold number of erase/write cycles, refreshing the data in the first memory block.

2. The method of claim 1, wherein determining that the data written in the first memory block needs to be refreshed further comprises:

determining that the data is written in the first memory block, without having been refreshed, for at least a threshold period of time.

3. The method of claim 1, wherein refreshing the data in the first memory block further comprises:

reading the data from the first memory block; and

rewriting the data to the first memory block.

4. The method of claim 1, wherein the threshold period of time is based on a number of erase/write cycles endured by the first memory block.

5. The method of claim 1, wherein the data is transient data.

6. The method of claim 1, wherein:

the first retention region is a low retention region; and

the second retention region is a medium retention region.

7. The method of claim 1, wherein:

the first retention region is configured to store data having a first expected storage duration;

the second retention region is configured to store data having a second expected storage duration; and

the first expected storage duration is equal to or less than the second expected storage duration.

8. The method of claim 1, wherein the NAND flash memory is a semi-volatile memory.

9. A flash memory device comprising:

a NAND flash memory that is portioned into a plurality of retention regions, wherein the plurality of retention regions includes a first retention region and a second retention region; and

a memory controller configured to

write data in a first memory block of the first retention region;

determine that the data written in the first memory block needs to be refreshed; and

based on determining that the data written in the first memory block needs to be refreshed,

(i) if the first memory block has endured at least a threshold number of erase/write cycles, relocate the data from the first memory block to a second memory block of the second retention region, and

(ii) if the first memory block has endured less than the threshold number of erase/write cycles, refresh the data in the first memory block.

10. The flash memory device of claim 9, wherein the memory controller is further configured to determine that the data written in the first memory block needs to be refreshed by:

determining that the data is written in the first memory block, without having been refreshed, for at least a threshold period of time.

11. The flash memory device of claim 9, wherein the memory controller is further configured to refresh the data in the first memory block by:

reading the data from the first memory block; and

rewriting the data to the first memory block.

12. The flash memory device of claim 9, wherein the threshold period of time is based on a number of write/erase cycles endured by the first memory block.

13. The flash memory device of claim 9, wherein the data is transient data.

14. The flash memory device of claim 9, wherein:

the first retention region is a low retention region; and

the second retention region is a medium retention region.

15. The flash memory device of claim 9, wherein:

the first retention region is configured to store data having a first expected storage duration;

the second retention region is configured to store data having a second expected storage duration; and

the first expected storage duration is equal to or less than the second expected storage duration.

16. The flash memory device of claim 9, wherein the NAND flash memory is a semi-volatile memory.

17. The flash memory device of claim 9, wherein the NAND flash memory is implemented on a single chip.