Systems and methods for speculative signal equalization

• US 8,121,186 B2
• Filed: 06/06/2008
• Issued: 02/21/2012
• Est. Priority Date: 06/06/2008
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Chmelar, Erik, Ito, Choshu, Loh, William
• Primary Examiner(s): Burd, Kevin M.
• Assistant Examiner(s): Haider, Syed
• Application Number:
  US12/134,501
• Publication Number:
  US 20090304066A1
• Time in Patent Office: 1,355 Days
• Field of Search: 375/229, 375/232, 375/233, 375/265, 375/317, 375/345, 375/348, 375/350, 375/359, 375/373, 341/118, 341/120, 341/155, 341/159, 341/160, 341/161
• US Class Current: 375/233
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
• CPC Class Codes: H03M 1/367 Non-linear conversion
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

Claims

1. A decision feedback equalizer circuit, the circuit comprising:

a comparator, wherein the comparator is operable to compare an input with a selected adjustment value corresponding to a first bit period, and to provide a decision output based at least in part on the comparison of the input with the selected adjustment value;

a storage device operable to store a prior output of the comparator;

a first adjustment calculation circuit that is operable to calculate a first adjustment feedback value based at least in part on the prior output of the comparator;

a second adjustment calculation circuit that is operable to calculate a second adjustment feedback value based at least in part on the prior output of the comparator;

a selector circuit, wherein the selector circuit is operable to select the first adjustment feedback as the selected adjustment value when the decision output is the first logic level, and wherein the selector circuit is operable to select the second adjustment feedback as the selected adjustment value when the decision output is the second logic level; and

wherein at least one of the first adjustment feedback value and the second adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output.

2. The circuit of claim 1, wherein the first adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output.

3. The circuit of claim 2, wherein the bit period precedes a bit period of the decision output.

4. The circuit of claim 3, wherein the prior output is a first prior output, wherein the bit period is a first bit period, wherein the first adjustment feedback value is generated at least in part based on the first prior output and a second prior output of the comparator, wherein the storage device stores both the first prior output and the second prior output, and wherein the first adjustment calculation circuit multiplies the first prior output by a first inter symbol interference value corresponding to the first bit period and multiplies the second prior output by a second inter symbol interference value corresponding to a second bit period, and wherein the first adjustment feedback value includes a sum of the product of multiplying the first prior output by the first inter symbol interference value and the product of multiplying the second prior output by the second inter symbol interference value.

5. The circuit of claim 1, wherein the second adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output.

6. The circuit of claim 5, wherein the prior output is a first prior output, wherein the bit period is a first bit period, wherein the second adjustment feedback value is calculated at least in part based on the first prior output and a second prior output of the comparator, wherein the storage device stores both the first prior output and the second prior output, and wherein the first adjustment calculation circuit multiplies the first prior output by a first inter symbol interference value corresponding to the first bit period and multiplies the second prior output by a second inter symbol interference value corresponding to a second bit period, and wherein the first adjustment feedback value includes a sum of the product of multiplying the first prior output by the first inter symbol interference value and the product of multiplying the second prior output by the second inter symbol interference value.

7. The circuit of claim 1, wherein the selector is a multiplexer, and wherein a select input of the multiplexer is driven by the decision output.

8. The circuit of claim 1, wherein the circuit further includes a synchronizing register, and wherein the selected adjustment value is synchronized by the synchronizing register.

21. The circuit of claim 1, wherein the circuit is implemented as part of a storage device.

22. The circuit of claim 1, wherein the circuit is implemented as part of a wireless data transfer device.

9. An analog to digital conversion circuit, the circuit comprising:

an analog input;

a comparator bank, wherein the comparator bank is operable to receive a reference indicator, and wherein the comparator bank is operable to provide a decision output based at least in part on a comparison of the analog input with a reference threshold at a time governed at least in part by the reference indicator; and

a range selection filter, wherein the range selection filter includes;

a first adjustment calculation circuit that is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, wherein the first adjustment feedback value includes a prior output of the comparator bank multiplied by an inter symbol interference value corresponding to a bit period of the prior output;

a second adjustment calculation circuit that is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level; and

a selector circuit, wherein the selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and wherein the selector circuit selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

10. The circuit of claim 9, wherein the comparator bank includes a single comparator, wherein the reference indicator is a voltage offset, and wherein the reference threshold is a reference voltage plus the voltage offset.

11. The circuit of claim 10, wherein the first adjustment calculation circuit and the second adjustment calculation circuit are driven by a storage device, wherein the storage device is operable to store the prior output of the comparator bank, and wherein the first adjustment feedback value is calculated based at least in part on the prior output of the comparator bank.

12. The circuit of claim 11, wherein the bit period precedes a bit period of the decision output.

13. The circuit of claim 12, wherein the prior output is a first prior output, wherein the bit period is a first bit period, wherein the first adjustment feedback value is generated at least in part based on the first prior output and a second prior output of the comparator bank, wherein the storage device stores both the first prior output and the second prior output, and wherein the first adjustment calculation circuit multiplies the first prior output by a first inter symbol interference value corresponding to the first bit period and multiplies the second prior output by a second inter symbol interference value corresponding to a second bit period, and wherein the first adjustment feedback value includes a sum of the product of multiplying the first prior output by the first inter symbol interference value and the product of multiplying the second prior output by the second inter symbol interference value.

14. The circuit of claim 11, wherein the second adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output.

15. The circuit of claim 14, wherein the prior output is a first prior output, wherein the bit period is a first bit period, wherein the second adjustment feedback value is calculated at least in part based on the first prior output and a second prior output of the comparator bank, wherein the storage device stores both the first prior output and the second prior output, and wherein the first adjustment calculation circuit multiplies the first prior output by a first inter symbol interference value corresponding to the first bit period and multiplies the second prior output by a second inter symbol interference value corresponding to a second bit period, and wherein the first adjustment feedback value includes a sum of the product of multiplying the first prior output by the first inter symbol interference value and the product of multiplying the second prior output by the second inter symbol interference value.

16. The circuit of claim 10, wherein the selector is a multiplexer, and wherein a select input of the multiplexer is driven by the decision output.

17. The circuit of claim 10, wherein the selector includes a first encoder, a second encoder, and a multiplexer;

wherein the first encoder receives the first adjustment feedback value and generates a first speculative encoder output based on the first adjustment feedback value and a speculation that the decision output is the first logic level;

wherein the second encoder receives the second adjustment feedback value and generates a second speculative encoder output based on the second adjustment feedback value and a speculation that the decision output is the second logic level;

wherein the first speculative encoder output and the second speculative encoder output are provided as inputs to the multiplexer; and

wherein the multiplexer provides the first speculative encoder output as the reference indicator when the decision output is the first logic level; and

wherein the multiplexer provides the second speculative encoder output as the reference indicator when the decision output is the second logic level.

23. The circuit of claim 9, wherein the circuit is implemented as part of a storage device.

24. The circuit of claim 9, wherein the circuit is implemented as part of a wireless data transfer device.

18. A communication system, the system comprising:

a receiver including an analog to digital converter, wherein the analog to digital converter includes;

a comparator bank, wherein the comparator bank is operable to receive a reference indicator, and wherein the comparator bank is operable to provide a decision output based at least in part on a comparison of the analog input with a reference threshold at a time governed at least in part by the reference indicator; and

a range selection filter, wherein the range selection filter includes;

a first adjustment calculation circuit that is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level;

a second adjustment calculation circuit that is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level, wherein the second adjustment feedback value includes a prior output of the comparator bank multiplied by an inter symbol interference value corresponding to a bit period of the prior output;

wherein the first adjustment calculation circuit and the second adjustment calculation circuit are driven by a storage device, wherein the storage device is operable to store the prior output of the comparator bank; and

a selector circuit, wherein the selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and wherein the selector circuit selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

19. The communication system of claim 18, wherein the communication system is a storage system operable to transfer information via a storage medium.

20. The communication system of claim 18, wherein the communication system is a wireless communication system, and wherein the wireless communication system is operable to transfer information via a wireless medium.