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Dispatch mechanism for dispatching instructions from a host processor to a co-processor

  • US 8,122,229 B2
  • Filed: 09/12/2007
  • Issued: 02/21/2012
  • Est. Priority Date: 09/12/2007
  • Status: Active Grant
First Claim
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1. A method comprising:

  • dispatching instructions of an executable file from a manufactured host processor, said host processor having a first instruction set that is fixed such that it is not modifiable by a consumer, to a heterogeneous co-processor, wherein said heterogeneous co-processor is not implemented on a same integrated circuit as said manufactured host processor, wherein said heterogeneous co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor to have any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the first instruction set, and wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set;

    executing, by said host processor, a first portion of instructions of the executable file;

    said dispatching comprising writing, by said host processor, an address of a second portion of instructions of said executable file to a designated portion of a memory, said second portion of instructions comprising said at least one of said extended instructions included in said executable file, where said memory comprises a common global physical memory space that is accessible by each of said host processor and said heterogeneous co-processor;

    detecting, by said co-processor, said address of said instructions in the designated portion of memory; and

    executing, by said co-processor, said second portion of instructions;

    wherein said address of said instructions comprises a global physical address, said method further comprising accessing said designated portion of memory by said host processor and by said co-processor, wherein said accessing comprises;

    maintaining cache coherency between said host processor and said co-processor to ensure that an up-to-date value of the designated portion of memory is accessed.

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