Dispatch mechanism for dispatching instructions from a host processor to a co-processor

• US 8,122,229 B2
• Filed: 09/12/2007
• Issued: 02/21/2012
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Brewer, Tony, Wallach, Steven J.
• Primary Examiner(s): Kindred, Alford
• Assistant Examiner(s): Moll, Jesse R
• Application Number:
  US11/854,432
• Publication Number:
  US 20090070553A1
• Time in Patent Office: 1,623 Days
• Field of Search: 712/34, 712/43
• US Class Current: 712/34
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor'"'"'s instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.

Claims

1. A method comprising:

dispatching instructions of an executable file from a manufactured host processor, said host processor having a first instruction set that is fixed such that it is not modifiable by a consumer, to a heterogeneous co-processor, wherein said heterogeneous co-processor is not implemented on a same integrated circuit as said manufactured host processor, wherein said heterogeneous co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor to have any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the first instruction set, and wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set;

executing, by said host processor, a first portion of instructions of the executable file;

said dispatching comprising writing, by said host processor, an address of a second portion of instructions of said executable file to a designated portion of a memory, said second portion of instructions comprising said at least one of said extended instructions included in said executable file, where said memory comprises a common global physical memory space that is accessible by each of said host processor and said heterogeneous co-processor;

detecting, by said co-processor, said address of said instructions in the designated portion of memory; and

executing, by said co-processor, said second portion of instructions;

wherein said address of said instructions comprises a global physical address, said method further comprising accessing said designated portion of memory by said host processor and by said co-processor, wherein said accessing comprises;

maintaining cache coherency between said host processor and said co-processor to ensure that an up-to-date value of the designated portion of memory is accessed.

2. The method of claim 1 further comprising:

addressing, by said host processor, said designated portion of memory by a globally shared virtual address; and

addressing, by said co-processor, said designated portion of memory by said globally shared virtual address, wherein global virtual address spaces of the host processor and the co-processor are identical.

3. The method of claim 1 wherein said address of said instructions comprises a globally shared virtual address within a global virtual address space that is identical for the host processor and the co-processor, wherein said accessing further comprises:

generating said globally shared virtual address; and

translating the globally shared virtual address into said global physical address.

4. The method of claim 1 wherein said host processor and said co-processor share a common global virtual address space;

and wherein said host processor and said co-processor share a common global physical address space.

5. The method of claim 1 further comprising:

writing one instruction at a time by said host processor to said designated portion of memory.

6. The method of claim 1 wherein said writing said address of said second portion of instructions to said designated portion of memory comprises:

writing an address for a first instruction of a block of instructions by the host processor to said designated portion of memory.

7. The method of claim 1 wherein said writing said address of said second portion of instructions to said designated portion of memory comprises:

instructing, by an operating system running on the host processor, an input/output (I/O) system to read said instructions from disk and write said instructions to said designated portion of memory.

8. The method of claim 1 wherein said detecting, by said co-processor, comprises:

monitoring, by the co-processor, a value in an issue memory structure;

detecting, by the co-processor, a predefined value in said issue memory structure that is indicative of said second portion of instructions at said address written in the designated portion of memory are ready for execution by said co-processor;

after writing said address of the second portion of instructions of said executable file to the designated portion of memory, writing, by the host processor, the predefined value to the issue memory structure for triggering processing of the second portion of instructions by the co-processor; and

responsive to detecting said predefined value in the issue memory structure, said co-processor performing said executing of said second portion of instructions at said address written in the designated portion of memory.

9. The method of claim 8 wherein the designated portion of memory comprises a command memory structure, the method further comprising:

writing information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure prior to said host processor writing said address of said second portion of instructions of said executable file to said command memory structure;

writing said information to said issue memory structure to indicate that the co-processor possesses ownership of the command memory structure after said host processor writing said address of said second portion of instructions of said executable file to said command memory structure and prior to said co-processor executing said second portion of instructions; and

writing said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure after said co-processor executing said second portion of instructions.

10. The method of claim 9 further comprising:

monitoring, by said co-processor, cache coherency requests sent from the host processor to the co-processor for said issue memory structure.

11. The method of claim 1 wherein said first portion of instructions of the executable file are coded for the instruction set of said host processor;

and wherein said second portion of instructions of said executable file are coded for said extended instruction set instruction set of said co-processor.

12. The method of claim 1 wherein said executable file comprises a single .out executable file or a single .exe executable file.

13. The method of claim 10 wherein said monitoring cache coherency requests comprises:

monitoring both read and write requests.

14. The method of claim 1 wherein said first instruction set of the host processor does not include a native instruction for dispatching said second portion of instructions of the executable file to said heterogeneous co-processor.

15. The method of claim 14 wherein said writing said address of the second portion of instructions by said host processor comprises said host processor using one or more instructions included in the first instruction set for performing said writing.

16. The method of claim 1 wherein said host processor and said heterogeneous co-processor are communicatively interconnected via a bus.

17. A method comprising:

executing, by a host processor, a first portion of instructions of an executable file;

dispatching instructions of the executable file from the host processor to an external heterogeneous co-processor that is external to an integrated circuit on which said host processor is implemented, wherein said host processor has a first instruction set and wherein said heterogeneous co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the first instruction set, wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set;

wherein said dispatching comprises writing, by said host processor, an address of the at least one extended instruction included in said executable file to a designated portion of memory;

detecting, by said co-processor, said address of said the at least one extended instruction in the designated portion of memory;

writing information to said designated portion of memory to specify one of the plurality of predefined extended instruction sets to be employed on the co-processor for processing the at least one extended instruction; and

executing, by said co-processor, said at least one extended instruction.

18. The method of claim 17 where said memory comprises a common global physical memory space shared by said host processor and said heterogeneous co-processor.

19. The method of claim 18 further comprising:

accessing said designated portion of memory by said host processor and by said co-processor, wherein said accessing comprises maintaining cache coherency between said host processor and said co-processor to ensure that an up-to-date value of the designated portion of memory is accessed.

20. The method of claim 17 wherein said host processor is a manufactured processor having a fixed instruction set that is not modifiable by a consumer.

21. The method of claim 20 wherein said fixed instruction set of the host processor does not include a native instruction for dispatching said at least one of said extended instructions that is included in the executable file to said heterogeneous co-processor.

22. The method of claim 21 wherein said writing said address of the at least one extended instruction by said host processor comprises said host processor using one or more instructions included in the host processor'"'"'s fixed instruction set for performing said writing.

23. A method comprising:

issuing extended instructions of an executable file for processing by a co-processor, wherein a host processor and said co-processor each process a portion of instructions of said executable file, and wherein the host processor is a manufactured processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, and wherein the co-processor is reconfigurable to have any of a plurality of predefined extended instruction sets for extending the fixed instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the host processor'"'"'s instruction set, wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the host processor'"'"'s instruction set, and wherein the host processor'"'"'s instruction set does not include a native instruction for dispatching said extended instructions to said co-processor;

monitoring, by the co-processor, an issue memory structure;

said issuing comprises writing, by the host processor, to a command memory structure an address of at least one extended instruction included in the executable file to be processed by the co-processor;

writing, by the host processor, a predefined value to the issue memory structure for triggering processing of the at least one extended instruction; and

responsive to detecting said predefined value in the issue memory structure, said co-processor processing the at least one extended instruction included in the executable file, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

24. The method of claim 23 the method further comprising:

maintaining cache coherency between said co-processor and said host processor.

25. The method of claim 23 wherein said issue memory structure comprises information indicating whether current ownership of the command memory structure is possessed by said host processor or by said co-processor, the method further comprises:

writing, by said host processor, said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure prior to said host processor writing said address of said instructions of said executable file to said command memory structure;

writing said information to said issue memory structure to indicate that the co-processor possesses ownership of the command memory structure after said host processor writing said address of said instructions of said executable file to said command memory structure and prior to said co-processor executing said instructions; and

writing said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure after said co-processor executing said instructions.

26. The method of claim 23 further comprising:

initializing registers of the co-processor, wherein said initializing comprises writing data to said registers of the co-processor from said command memory structure.

27. The method of claim 23 wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined extended instruction sets, said method further comprising:

writing, by said host processor, information to said command memory structure to specify one of the plurality of predefined extended instruction sets to be employed on the co-processor for processing the instructions.

28. The method of claim 23 wherein said writing said address of the at least one extended instruction by said host processor comprises said host processor using one or more instructions included in the host processor'"'"'s predefined instruction set for performing said writing.

29. The method of claim 23 wherein said co-processor is external to an integrated circuit on which said host processor is implemented.

30. A method for issuing instructions of an executable file for processing by a co-processor, the method comprising:

executing said executable file on a manufactured host processor that is implemented on a first integrated circuit and that has a fixed instruction set that is not modifiable by a consumer;

monitoring, by the co-processor, an issue memory structure that is in a common global physical address space that is shared by said host processor and said co-processor, wherein the co-processor is implemented external to said first integrated circuit and has an extended instruction set that extends the instruction set of the host processor such that the extended instruction set provides extended instructions not natively supported by the host processor'"'"'s instruction set, and wherein the executable file includes at least one of said extended instructions and at least one instruction that is native to the host processor'"'"'s instruction set;

writing, by the host processor, to a command memory structure an address of the at least one extended instruction included in the executable file to be processed by the co-processor, wherein said command memory structure is in said common global physical address space that is shared by said host processor and said co-processor;

writing, by the host processor, a predefined value to the issue memory structure for triggering processing of the at least one extended instruction included in the executable file; and

responsive to detecting said predefined value in the issue memory structure, said co-processor processing the at least one extended instruction included in the executable file;

wherein said monitoring said issue memory structure comprises;

monitoring, by said co-processor, cache line activity of the issue memory structure, and

responsive to detecting cache line activity occurring in the issue memory structure, said co-processor determining whether the issue memory structure contains said predefined value for triggering processing of the at least one extended instruction addressed at the address in the command memory structure.

31. The method of claim 30 further comprising:

said host processor processing said at least one instruction included in said executable file that is native to the host processor'"'"'s instruction set.

32. The method of claim 30 wherein said writing, by the host processor, said predefined value to the issue memory structure triggers processing by the co-processor of the at least one extended instruction included in the executable file.

33. The method of claim 30 wherein said host processor'"'"'s instruction set does not include a native instruction for dispatching said at least one extended instruction included in the executable file to the co-processor;

and wherein said writing said address of the at least one extended instruction included in the executable file by said host processor comprises said host processor using one or more native instructions included in the host processor'"'"'s instruction set for performing said writing.

34. A method comprising:

processing instructions of an executable file by a system that comprises a manufactured host processor that is implemented on a first integrated circuit and having a predefined fixed instruction set that is not modifiable by a consumer, and a heterogeneous co-processor that is implemented external to said first integrated circuit and having an extended instruction set that extends said fixed instruction set of the host processor such that the extended instruction set provides extended instructions not natively supported by the host processor'"'"'s fixed instruction set, wherein the executable file comprises at least one segment of instructions that are native to the host processor'"'"'s fixed instruction set and at least one segment of said extended instructions;

maintaining cache coherency between the at least one host processor and the at least one heterogeneous co-processor;

writing to a command memory structure, by the host processor, a virtual address of a first instruction of the at least one segment of said extended instructions, wherein said host processor and said heterogeneous co-processor share a common global virtual address space; and

triggering the co-processor to begin execution of said at least one segment of said extended instructions at the virtual address by said host processor writing a value to an issue memory structure.

35. The method of claim 34 further comprising:

upon initiating said executable file for processing by said system, loading said instructions of said executable file into memory.

36. The method of claim 34 wherein the heterogeneous co-processor comprises dynamically reconfigurable logic, the method comprising:

configuring said dynamically reconfigurable logic to have said extended instruction set.

37. The method of claim 34 wherein said executable file requires both said host processor'"'"'s fixed instruction set and said extended instruction set to be executed.

38. The method of claim 34 where said command memory structure and said issue memory structure are in a common global physical memory space shared by the host processor and the co-processor.

39. The method of claim 34 wherein said host processor'"'"'s instruction set does not include a native instruction for dispatching said extended instructions included in the executable file to the heterogeneous co-processor;

and wherein said writing said virtual address by said host processor comprises said host processor using one or more native instructions included in the host processor'"'"'s instruction set for performing said writing.

40. A system comprising:

a plurality of processors comprising at least a manufactured host processor implemented on a first integrated circuit and a heterogeneous co-processor implemented external to said first integrated circuit, wherein the host processor has a predefined fixed instruction set that is not modifiable by a consumer and wherein the heterogeneous co-processor is reconfigurable to have any of a plurality of predefined extended instruction sets for extending the host processor'"'"'s instruction set such that each extended instruction set provides extended instructions not natively supported by the host processor'"'"'s instruction set, wherein the host processor'"'"'s instruction set does not include a native instruction for dispatching said extended instructions to said co-processor, and wherein the host processor processes instructions included in an executable file that are native to the host processor'"'"'s instruction set and said heterogeneous co-processor processes at least one of said extended instructions included in the executable file;

a communication bus for communicatively interconnecting said host processor on said first integrated circuit with said external heterogeneous co-processor;

a command memory structure to which said host processor identifies said at least one of said extended instructions of the executable file that are to be processed by the co-processor; and

an issue memory structure that indicates which of said host processor and heterogeneous co-processor possesses ownership of said command memory structure, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

41. The system of claim 40 wherein said host processor writes a predefined value to the issue memory structure for triggering processing of the at least one of said extended instructions identified in the command memory structure by the heterogeneous co-processor, and wherein said heterogeneous co-processor monitors the issue memory structure, and responsive to detecting said predefined value in the issue memory structure, said co-processor processes the at least one of said extended instructions of the executable file that are identified in the command memory structure.

42. The system of claim 41 wherein said host processor and said heterogeneous co-processor each comprise respective local caches, and wherein cache coherency is maintained between said host processor and said heterogeneous co-processor;

wherein said heterogeneous co-processor monitors cache line activity of the issue memory structure to detect information being written to the issue memory structure indicating that ownership of the command memory structure has changed to be possessed by the co-processor, wherein responsive to detecting said information in the issue memory structure, said co-processor processes the at least one of said extended instructions of the executable file that are in the command memory structure.

43. The system of claim 40 wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of the plurality of predefined extended instruction sets, wherein said host processor writes information to said command memory structure to specify one of the plurality of predefined extended instruction sets to be employed on the co-processor for processing the at least one of said extended instructions included in the executable file.

44. A system comprising:

at least one manufactured host processor that is implemented on a first integrated circuit and having a fixed instruction set that is not modifiable by a consumer and comprising a first main memory;

at least one heterogeneous co-processor that is implemented external to said first integrated circuit and having a second instruction set that extends said host processor'"'"'s instruction set such that the extended instruction set provides extended instructions not natively supported by the host processor'"'"'s fixed instruction set and said at least one heterogeneous co-processor comprising a second main memory, wherein said first main memory and said second main memory are in a common global physical memory space, and wherein said host processor'"'"'s fixed instruction set does not include a native instruction for dispatching said extended instructions to said at least one heterogeneous co-processor;

said at least one host processor and said at least one heterogeneous co-processor each comprising a respective local cache, wherein cache coherency is maintained between the at least one host processor and at least one heterogeneous co-processor; and

a designated portion of at least one of said first main memory and said second main memory, wherein when the at least one host processor is executing an executable file that includes instructions natively supported by the host processor'"'"'s fixed instruction set and at least one of said extended instructions, said at least one host processor uses at least one instruction of its fixed instruction set to store to said designated portion identification of said at least one of said extended instructions included in said executable file for processing by said at least one heterogeneous co-processor.

45. The system of claim 44 wherein said at least one of said extended instructions of said executable file are coded for said second instruction set;

and wherein said at least one host processor is operable to execute other instructions of said executable file that are coded for said host processor'"'"'s fixed instruction set.

46. The system of claim 44 wherein the co-processor comprises reconfigurable logic for reconfiguring the co-processor to have any of a plurality of predefined extended instruction sets as said second instruction set.

47. The system of claim 44 further comprising:

a communication bus for communicatively interconnecting said at least one host processor on said first integrated circuit with said at least one external heterogeneous co-processor.

48. A method for executing instructions of an executable file by a manufactured host processor implemented on a first integrated circuit and a co-processor that is implemented external to said first integrated circuit, wherein said manufactured host processor has a fixed instruction set that is not modifiable by a consumer and the co-processor has an extended instruction set that includes extended instructions not natively supported by the fixed instruction set of the host processor, wherein said executable file includes at least one instruction of said host processor'"'"'s fixed instruction set and at least one of said extended instructions, and wherein the host processor'"'"'s fixed instruction set does not include a native instruction for issuing said at least one of said extended instructions to said at least one heterogeneous co-processor, the method comprising:

monitoring, by the co-processor, an issue memory structure, wherein said monitoring said issue memory structure comprises;

monitoring, by said co-processor, cache line activity of an issue memory structure, and

responsive to detecting cache line activity occurring in the issue memory structure, said co-processor determining whether the issue memory structure contains a predefined value for triggering processing of said at least one of said extended instructions of the executable file that is addressed at an address contained in a command memory structure; and

responsive to detecting by the co-processor said predefined value in the issue memory structure, said co-processor processing the at least one of said extended instructions of the executable file that is addressed at the address contained in the command memory structure, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

49. The method of claim 48 wherein the co-processor comprises reconfigurable logic that is reconfigurable to have any of a plurality of predefined extended instruction sets for extending the instruction set of the host processor.

50. The method of claim 49 further comprising:

reconfiguring the reconfigurable logic of the co-processor to have a desired one of the plurality of predefined extended instruction sets for processing the at least one of said extended instructions of the executable file.

51. The method of claim 50 further comprising:

determining, from the executable file, the desired one of the plurality of predefined extended instruction sets.

52. A method comprising:

executing, by a manufactured host processor that is implemented on a first die, a first portion of instructions of an executable file, wherein said manufactured host processor has a first instruction set that is fixed such that it is not modifiable by a consumer;

dispatching instructions of the executable file from the host processor to a co-processor that is not implemented on said first die, wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides instructions not natively supported by the first instruction set, wherein at least one of the instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set, and wherein said first instruction set does not natively support dispatching of the at least one extended instruction to said heterogeneous co-processor;

said dispatching comprising writing, by said host processor, an address of the at least one extended instruction of said executable file to a designated portion of a shared memory;

detecting, by said co-processor, said address of the at least one extended instruction in the designated portion of memory; and

executing, by said co-processor, said at least one extended instruction.

53. The method of claim 52 wherein the first portion of instructions of the executable file includes an instruction that is natively supported by the first instruction set to cause the host processor to perform said writing.

54. The method of claim 53 further comprising:

compiling, by a compiler, said executable file, wherein said compiling includes said first portion of instructions and said at least one extended instruction in the executable file.

55. The method of claim 54 wherein said compiling further comprises:

including, in said executable file, an identification of one of said plurality of predefined extended instruction sets that includes said at least one extended instruction that is included in the executable file.

56. The method of claim 55 further comprising:

determining whether the co-processor possesses the one of said plurality of predefined extended instruction sets that is identified in the executable file; and

when determined that said co-processor does not possess the identified one of said plurality of predefined extended instruction sets, loading said identified one of said plurality of predefined extended instruction sets to the co-processor.

57. The method of claim 54 wherein said compiling further comprises:

including, in said executable file, an instruction an instruction that is natively supported by the first instruction set to cause the host processor to perform said writing.