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One time programmable memory test structures and methods

  • US 8,122,307 B1
  • Filed: 06/27/2007
  • Issued: 02/21/2012
  • Est. Priority Date: 08/15/2006
  • Status: Active Grant
First Claim
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1. A programmable memory device, comprising:

  • support circuitry; and

    a memory array connected to the support circuitry, the memory array comprising;

    a plurality of one time programmable (OTP) memory cells operable to store data under control of the support circuitry; and

    at least one multiple time programmable (MTP) memory cell operable to store data and to test operations of the support circuitry associated with a subset of the plurality of the OTP memory cells.

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