One time programmable memory test structures and methods

• US 8,122,307 B1
• Filed: 06/27/2007
• Issued: 02/21/2012
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Lindhorst, Chad A., Humes, Todd E., Horch, Andrew E., Allen, Ernest III
• Primary Examiner(s): Gaffin, Jeffrey A
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US11/768,974
• Time in Patent Office: 1,700 Days
• Field of Search: None
• US Class Current: 714/719
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated “Not Usable”, while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.

Claims

1. A programmable memory device, comprising:

support circuitry; and

a memory array connected to the support circuitry, the memory array comprising;

a plurality of one time programmable (OTP) memory cells operable to store data under control of the support circuitry; and

at least one multiple time programmable (MTP) memory cell operable to store data and to test operations of the support circuitry associated with a subset of the plurality of the OTP memory cells.

2. The device of claim 1, in which

the at least one MTP memory cell is configured to be programmed with a test value and then to be read, for testing the support circuitry.

3. The device of claim 2, in which

the read test value and the programmed test value are compared for testing the support circuitry.

4. The device of claim 2, in which

the read test value is compared to an expected value for testing the support circuitry.

5. The device of claim 4, in which

the read test value and the expected test value include an analog range of values.

6. The device of claim 2, in which

the support circuitry includes a column multiplexer configured to read out test values.

7. The device of claim 1, in which

the support circuitry includes a High Voltage (HV) switch configured to provide a first voltage level for programming the OTP memory cells and the MTP memory cells, and a second voltage for erasing the MTP memory cells.

8. The device of claim 7, in which

the support circuitry includes a High Voltage (HV) driver configured to operate the high voltage switch.

9. The device of claim 1, in which

the support circuitry includes a charge pump configured to generate voltage levels to program the OTP memory cells within the memory array.

10. The device of claim 1, in which

the support circuitry includes a controller configured to program and address the memory array.

11. The device of claim 1, in which

the support circuitry includes a sense amplifier.

12. The device of claim 1, in which

the support circuitry includes a plurality of row drivers, each row driver configured to apply a voltage to a row of cells in the memory array.

13. The device of claim 1, further comprising

a line of the MTP memory cells wherein each MTP memory cell shares a row or a column with at least one of the plurality of OTP memory cells.

14. The device of claim 13, in which

the line is a row.

15. The device of claim 13, in which

the line is a column.

16. The device of claim 1 further comprising a second memory array controlled by the support circuitry, wherein operations associated with the support circuitry for the second array are tested using the MTP memory cells in the other array.

17. The device of claim 1, in which

the at least one MTP memory cell is programmed and read one at a time.

18. The device of claim 1, in which

a plurality of MTP memory cells are programmed concurrently.

19. The device of claim 1, in which

a plurality of MTP memory cells are read concurrently.

20. The device of claim 1, in which

a plurality of MTP memory cells are programmed and read one bit at a time.

21. The device of claim 1, in which

a plurality of MTP memory cells are programmed and read multiple bits at a time.

22. The device of claim 1, in which each MTP memory cell is placed randomly in the memory array.

23. The device of claim 22, in which each MTP memory cell is placed on a different row and a different column of the memory array.

24. The device of claim 1, in which:

each OTP memory cell and MTP memory cell comprises a floating gate pFET readout transistor, the readout transistor having a source coupled to a power source and a drain providing a drain current for determining a state of each of the OTP memory cells.

25. A method, comprising:

testing support circuitry for operations associated with controlling at least one multiple time programmable (MTP) memory cell in a memory array, wherein testing includes programming the at least one MTP memory cell;

determining a plurality of one-time programmable (OTP) memory cells in the memory array sharing a same row or column with the at least one MTP memory cell in the memory array as usable; and

reprogramming the at least one MTP memory cell for storing data with the OTP memory cells responsive to determining the memory array as usable.

26. The method of claim 25, wherein testing the support circuitry further comprises:

programming the at least one MPT memory cell with a test value;

reading a value from the at least one programmed MTP memory cell; and

comparing the read value with the test value to determine if the programming was successful.

27. The method of claim 26, in which the read value is defined as an analog range of values.

28. The method of claim 26, further comprising:

programming and reading the MTP memory cells one at a time.

29. The method of claim 26, further comprising:

programming the MTP memory cells concurrently.

30. The method of claim 26, further comprising:

reading the MTP memory cells concurrently.

31. The method of claim 26, further comprising:

programming and reading the MTP memory cells one bit at a time.

32. The method of claim 26, further comprising:

programming and reading the MTP memory cells multiple bits at a time.

33. The method of claim 25, further comprising:

programming the memory array responsive to determining the support circuitry as usable, and reprogramming the at least one MTP cell used for testing the support circuitry.

34. The method of claim 25, in which

testing the support circuitry utilizes a plurality of MTP memory cells, and reprogramming the plurality of MTP memory cells.

35. The method of claim 34, in which

the support circuitry is configured to support a column and a row of memory cells.

36. The method of claim 35, in which

the support circuitry includes a plurality of row driver, each row driver configured to apply a voltage to a row of cells in the memory array.

37. The method of claim 35, in which

the support circuitry includes a plurality of column multiplexer, each multiplexer configured to read out test values.

38. The method of claim 34, in which

a subset of the OTP memory cells and a subset of the MTP memory cells are arranged along a line.

39. The method of claim 38, in which

the line is a row.

40. The method of claim 38, in which

the line is a column.

41. The method of claim 25, the method further comprising:

placing each MTP memory cell on a different row and a different column within the memory array.

42. An article comprising a machine-readable non-transitory memory containing thereon instructions which, if executed by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit will result on the wafer, the integrated circuit suitable for being separated from the wafer to form a memory device, the memory device comprising:

at least one memory array comprising;

a plurality of one time programmable (OTP) memory cells, operable to store data;

and a plurality of multiple time programmable (MTP) memory cells, each operable to store data and associated with at least one of the plurality of OTP memory cells; and

support circuitry operable to control the plurality of OTP memory cells and the plurality of MTP memory test cells, in which at least a portion of the support circuitry can be pretested utilizing the plurality of MTP memory test cells.

43. The article of claim 42, in which

the plurality of MTP memory cells are configured to be programmed with a test value and then to be read, for testing the support circuitry.

44. The article of claim 43, in which

the read test value and the programmed test value are compared for testing the support circuitry.

45. The article of claim 43, in which

the read test value is compared to an expected value for testing the support circuitry.

46. The article of claim 45, in which

the read test value and the expected test value include an analog range of values.

47. The article of claim 42, in which each MTP memory cell is placed randomly in the memory array.

48. The article of claim 42, in which each MTP memory cell is placed on a different row and a different column of the memory array.

49. The article of claim 42, in which:

each OTP memory cell and MTP memory cell comprises a floating gate pFET readout transistor, the readout transistor having a source coupled to a power source and a drain providing a drain current for determining a state of each of the OTP memory cells.