Method and apparatus for processing failures during semiconductor device testing
First Claim
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1. Apparatus for testing a device under test (DUT), comprising:
- probes configured to connect electrically with pins of the DUT including pins that are output pins;
a memory; and
fail capture logic coupled to ones of the test probes and the memory, the fail capture logic configured to allow to be written into the memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin during a test of the DUT, wherein the fail capture logic is further configured to allow to be written into the memory an indication of only the first failure on a particular individual one of the output pins after an indication of the first failure has been written into the memory for a different individual one of the output pins.
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Abstract
Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.
89 Citations
20 Claims
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1. Apparatus for testing a device under test (DUT), comprising:
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probes configured to connect electrically with pins of the DUT including pins that are output pins; a memory; and fail capture logic coupled to ones of the test probes and the memory, the fail capture logic configured to allow to be written into the memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin during a test of the DUT, wherein the fail capture logic is further configured to allow to be written into the memory an indication of only the first failure on a particular individual one of the output pins after an indication of the first failure has been written into the memory for a different individual one of the output pins. - View Dependent Claims (2, 3, 4)
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5. Apparatus for testing a device under test (DUT), comprising:
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fail capture logic, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory; and analog-to-digital converter (ADC) logic coupled between the test probes and the fail capture logic, the ADC logic configured to sample voltages of test result signals, the test result signals derived from output signals of the output pins, wherein the fail capture logic includes detection logic and disable logic, wherein the apparatus includes control logic, and wherein; the detection logic is configured to indicate the failures on the output pins of the DUT; the control logic is configured to store failure indications in the memory; and the disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test. - View Dependent Claims (6, 7)
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8. A test assembly, comprising:
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a probe card assembly having test probes configured to contact pins of a device under test (DUT); test instruments having test channels coupled to a memory, each of the test channels including; fail capture logic, coupled to ones of the test probes contacting output pins of the pins, to allow to be written into the memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin during a test of the DUT, wherein the fail capture logic allows to be written into the memory an indication of only the first failure on a particular individual one of the output pins after an indication of the first failure has been written into the memory for a different individual one of the output pins. - View Dependent Claims (9, 10, 11, 12)
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13. A test assembly, comprising:
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a probe card assembly having test probes configured to contact pins of a device under test (DUT); test instruments having test channels coupled to a memory, each of the test channels including;
fail capture logic, coupled to at least one of the test probes contacting at least one output pin of the pins, to indicate only first failures on the at least one output pin during a test for storage in the memory,wherein the fail capture logic includes detection logic and disable logic, wherein the test instruments include control logic, and wherein; the detection logic is configured to indicate the failures on the at least one output pin; the control logic is configured to store failure indications in the memory; and the disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test, and wherein each of the test channels further includes; an analog-to-digital converter (ADC) coupled between the fail capture logic and the at least one output pin, the ADC configured to obtain at least one sample of a voltage of a test result signal, the test result signal being derived from an output signal of each of the at least one output pin. - View Dependent Claims (14, 15)
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16. A method of testing a device under test (DUT) using a probe card assembly, comprising:
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applying test signals to input pins of the DUT during a test via test probes supported on the probe card assembly; receiving test result signals derived from output pins of the DUT responsive to the test signals; and storing in a memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin, wherein the storing in a memory stores an indication of the first failure on a particular individual one of the output pins after an indication of the first failure has been stored in the memory for a different individual one of the output pins. - View Dependent Claims (17, 18, 19, 20)
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Specification