System and method of storing reliability data

• US 8,122,322 B2
• Filed: 07/31/2007
• Issued: 02/21/2012
• Est. Priority Date: 07/31/2007
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Miller, Michael Howard
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/831,045
• Publication Number:
  US 20090037644A1
• Time in Patent Office: 1,666 Days
• Field of Search: 714/766, 714/768
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2020/1836 using a Reed Solomon [RS] code
• CPC Class Codes: G11B 2220/2516 Hard disks
• CPC Class Codes: G11B 2220/63 wherein solid state memory is used as a supplementary storage medium to store auxiliary data for detecting or correcting errors on a main storage medium
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory.

Claims

1. A method comprising:

storing data at a first memory having a first non-volatile memory type;

determining error correction data related to the stored data; and

storing the error correction data, separately from the stored data, at a second memory having a second non-volatile memory type;

wherein the first non-volatile memory has a slower random access capability than the second non-volatile memory.

2. The method of claim 1, wherein the first non-volatile memory type comprises a magnetic disc and the second non-volatile memory type comprises a solid-state memory.

3. The method of claim 1, wherein the first non-volatile memory type is a non-volatile memory type selected from one of magnetic memory, optical memory, and magneto-optical memory.

4. The method of claim 1, wherein the second non-volatile memory type comprises a flash memory.

5. The method of claim 1, further comprising updating the error correction data in real time at the second memory when data is stored at the first memory.

6. The method of claim 1, further comprising determining error detection data related to the stored data, and storing the error detection data at the second memory.

7. The method of claim 6, wherein the error detection data comprises parity data.

8. The method of claim 6, further comprising:

retrieving the stored data from the first memory;

retrieving the error detection data related to the stored data from the second memory; and

determining whether an error has occurred based on retrieved data and error detection data.

9. The method of claim 1, wherein the error correction data is not stored in the first memory.

10. The method of claim 1, further comprising correcting data stored at the first memory based on the error correction data.

11. The method of claim 10, wherein the error correction data is not stored at the first memory.

12. The method of claim 1, further comprising storing the error correction data at the first memory during an idle period of the first memory.

13. The method of claim 1, wherein the first memory type and the second memory type are distinct.

14. A system comprising:

a first non-volatile memory of a first memory type to store data;

an error correction circuit to determine error correction data related to the data stored at the first non-volatile memory; and

a second non-volatile memory of a second memory type to store the error correction data separately form the data stored at the first non-volatile memory;

wherein the first non-volatile memory has a slower random access capability than the second non-volatile memory.

15. The system of claim 14, wherein the first non-volatile memory comprises a magnetic disc and the second non-volatile memory comprises a solid-state memory.

16. The system of claim 14, further comprising:

a controller coupled to the first non-volatile memory and the second non-volatile memory, wherein the controller manages data storage a data storage function of the first non-volatile memory and the second non-volatile memory;

a buffer coupled to the controller and that receives data; and

an interface connector that couples to a host device and to the buffer to provide data from the host device to the buffer.

17. The system of claim 16, further comprising a housing that connects to a chassis of the host device, wherein the first non-volatile memory, the second non-volatile memory, the controller, the buffer, and the interface connector are coupled to the housing.

18. The system of claim 16, wherein the system comprises a single data storage unit pluggable into the host device.

19. The system of claim 16, wherein the controller is programmed to execute a method comprising:

storing data at the first non-volatile memory;

determining error correction data related to the stored data; and

storing the error correction data at the second non-volatile memory.

20. A non-transitory computer readable medium having instructions to cause a processor to execute a method comprising:

determining error correction data associated with primary data, wherein the primary data is stored at a first non-volatile memory of a first memory type; and

storing the error correction data, separately from the primary data, at a second non-volatile memory of a second memory type;

wherein the first memory type has a slower random access capability than the second memory type.

21. The non-transitory computer readable medium of claim 20, wherein the error correction data is determined based on previously stored error correction data and the primary data.

22. The non-transitory computer readable medium of claim 20, wherein the method further comprises determining error detection data related to the primary data, and storing the error detection data at the second non-volatile memory.

23. The non-transitory computer readable medium of claim 20, wherein the error correction data is determined based at least partially on data stored at a plurality of independent memory regions of the first non-volatile memory.

24. The non-transitory computer readable medium of claim 20, wherein the method further comprises correcting the primary data based on the error correction data.