Specifying and validating untimed nets

• US 8,122,410 B2
• Filed: 11/05/2008
• Issued: 02/21/2012
• Est. Priority Date: 11/05/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DiLullo, Jack, Kalla, Ronald Nick, Meil, Gavin Balfour, Ritzinger, Jeffrey Mark
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US12/264,992
• Publication Number:
  US 20100115482A1
• Time in Patent Office: 1,203 Days
• Field of Search: 716/107, 716/108, 716/113, 716/134
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

In accordance with an aspect of the present invention, specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical Design by correlating latches and chip-level nets. This allows the testing process to become closed-loop. Design and simulation time is also greatly reduced due to the accessibility of RTL design.

Claims

1. A method of modeling an integrated circuit design, an integrated circuit having the integrated circuit design being operable to perform intended functions, the method comprising:

creating a register transfer level design of the integrated circuit, the register transfer level design including an untimed net, wherein the register transfer level design further includes a functional macro connected to the untimed net;

associating a timing parameter to the untimed net; and

creating a physical design of the integrated circuit based on the register transfer level design, wherein the register transfer level design includes a physical component and the untimed net, and wherein the physical component corresponds to the functional macro and is connected to the untimed net.

2. The method of claim 1, further comprising:

associating a second timing parameter, wherein in creating the register transfer level design of the integrated circuit the register transfer level design further includes a timed net, and wherein in associating the second timing parameter comprises associating a second timing parameter to the timed net.

3. The method of claim 1, wherein in creating the physical design of the integrated circuit based on the register transfer level design, the timing parameter remains associated to the untimed net.

4. The method of claim 1, further comprising:

performing a verification of the register transfer level design of the integrated circuit using the timing parameter to verify that the integrated circuit is operable to perform the intended functions.

5. The method of claim 1, further comprising:

performing static timing analysis on the physical design of the integrated circuit.

6. A system for modeling an integrated circuit design, an integrated circuit having the integrated circuit design being operable to perform intended functions, the system comprising:

a register transfer level design portion operable to create a register transfer level design of the integrated circuit such that the register transfer level design includes an untimed net, wherein the register transfer level design further includes a functional macro connected to the untimed net;

a timing parameter portion operable to associate a timing parameter to the untimed net; and

a physical design portion operable to create a physical design of the integrated circuit based on the register transfer level design, wherein the register transfer level design includes a physical component and the untimed net, and wherein the physical component corresponds to the functional macro and is connected to the untimed net.

7. The system of claim 6, wherein the timing parameter portion is further operable to associate a second timing parameter, wherein the register transfer level design portion is further operable to create the register transfer level design of the integrated circuit such that the register transfer level design further includes a timed net, and wherein the timing parameter portion is operable to associate the second timing parameter to the timed net.

8. The system of claim 6, wherein the physical design portion is further operable to create the physical design of the integrated circuit based on the register transfer level design such that the timing parameter remains associated to the untimed net.

9. The system of claim 6, further comprising:

a verification portion operable to perform a verification of the register transfer level design of the integrated circuit using the timing parameter to verify that the integrated circuit is operable to perform the intended functions.

10. The system of claim 6, further comprising:

a static timing analysis portion operable to perform static timing analysis on the physical design of the integrated circuit.

11. A data processing system program product for executing instructions in a data processing system, the data processing system program product comprising a data processing system-readable storage medium having data processing system-readable program code embodied in the medium, the data processing system-readable program code being operable to instruct the data processing system to perform a method of modeling an integrated circuit design, an integrated circuit having the integrated circuit design being operable to perform intended functions, the method comprising:

creating a register transfer level design of the integrated circuit, the register transfer level design including an untimed net, wherein the register transfer level design further includes a functional macro connected to the untimed net;

associating a timing parameter to the untimed net; and

creating a physical design of the integrated circuit based on the register transfer level design, wherein the register transfer level design includes a physical component and the untimed net, and wherein the physical component corresponds to the functional macro and is connected to the untimed net.

12. The data processing system program product of claim 11, wherein the data processing system-readable program code is further operable to instruct the data processing system to perform a method further comprising:

associating a second timing parameter, wherein in creating the register transfer level design of the integrated circuit the register transfer level design further includes a timed net, and wherein in associating the second timing parameter comprises associating a second timing parameter to the timed net.

13. The data processing system program product of claim 11, wherein in creating the physical design of the integrated circuit based on the register transfer level design, the timing parameter remains associated to the untimed net.

14. The data processing system program product of claim 11, wherein the data processing system-readable program code is further operable to instruct the data processing system to:

perform a verification of the register transfer level design of the integrated circuit using the timing parameter to verify that the integrated circuit is operable to perform the intended functions.

15. The data processing system program product of claim 11, wherein the data processing system-readable program code is further operable to instruct the data processing system to:

perform static timing analysis on the physical design of the integrated circuit.