Integrated circuit packaging system with interposer

• US 8,124,451 B2
• Filed: 09/21/2007
• Issued: 02/28/2012
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Song, Sungmin, Lee, SeongMin, Ko, WonJun
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US11/859,359
• Publication Number:
  US 20090079091A1
• Time in Patent Office: 1,621 Days
• Field of Search: 438/458, 438/461, 438/109, 438/462, 298/30, 298/52, 257/777, 257/E23.062, 257/787
• US Class Current: 438/109
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center.

Claims

1. A method of manufacturing an integrated circuit packaging system comprising:

fabricating an interposer array having an access opening;

fabricating a base package substrate sheet having system interconnects on lower surface contacts;

attaching a first integrated circuit die over the base package substrate sheet;

attaching a second integrated circuit die over the first integrated circuit die;

mounting the interposer array over the first integrated circuit die; and

the second integrated circuit die;

molding an encapsulant, for covering the first integrated circuit die, the second integrated circuit die, and the base package substrate sheet, through the access opening including a top portion of the interposer array exposed from the encapsulant; and

singulating a base package from the base package substrate sheet and the interposer array by singulating the interposer array, substantially through the center of the access opening, and the base package substrate sheet, between the system interconnects, with a singulation device including exposing an interposer having recessed edges and corners exposed on a singulation edge.

2. The method as claimed in claim 1 further comprising coupling electrical interconnects through the access opening between the interposer array and the base package substrate sheet.

3. The method as claimed in claim 1 wherein molding the encapsulant through the access opening includes forming a base package array.

4. The method as claimed in claim 1 wherein mounting the second integrated circuit die over the first integrated circuit die includes coupling an electrical interconnect between the second integrated circuit die and the base package substrate sheet.

5. The method as claimed in claim 1 further comprising forming a contact array on the interposer array including interposer bonding contacts, interposer pin pads, interposer contacts, or a combination thereof.

6. A method of manufacturing an integrated circuit packaging system comprising:

fabricating an interposer array having an access opening including forming an interposer bonding contact adjacent to the access opening;

fabricating a base package substrate sheet having system interconnects on lower surface contacts including forming an upper surface contact on the base package substrate sheet;

attaching a first integrated circuit die over the base package substrate sheet including applying an adhesive between the base package substrate sheet and the first integrated circuit die;

attaching a second integrated circuit die over the integrated circuit die including applying an adhesive between the second integrated circuit die and the first integrated circuit die;

mounting the interposer array over the first integrated circuit die and the second integrated circuit die including applying the adhesive between the interposer array and the second integrated circuit die;

molding an encapsulant, for covering the first integrated circuit die, the second integrated circuit die, and the base package substrate sheet, through the access opening including a top portion of the interposer array exposed from the encapsulant; and

singulating a base package from the base package substrate sheet and the interposer array by singulating the interposer array, substantially through the center of the access opening, and the base package substrate sheet, between the system interconnects, with a singulation device including exposing an interposer having recessed edges and corners exposed on a singulation edge.

7. The method as claimed in claim 6 further comprising coupling electrical interconnects through the access opening between the interposer array and the base package substrate sheet including coupling the second integrated circuit die to the first integrated circuit die, the base package substrate sheet, the interposer array, or a combination thereof.

8. The method as claimed in claim 6 wherein molding the encapsulant through the access opening includes forming a base package array including encasing an electrical interconnect and a portion of the interposer array.

9. The method as claimed in claim 6 wherein mounting the second integrated circuit die over the first integrated circuit die in which mounting the second integrated circuit die includes coupling an electrical interconnect between the second integrated circuit die and the base package substrate sheet for forming an electrical connection between the first integrated circuit die, the second integrated circuit die, the base package substrate sheet, the interposer array, or a combination thereof.

10. The method as claimed in claim 6 further comprising forming a contact array on the interposer array including interposer bonding contacts, interposer pin pads, interposer contacts, or a combination thereof including molding the encapsulant over the interposer bonding contacts and not on the interposer pin pads or the interposer contacts.