Non-volatile memory device

• US 8,124,968 B2
• Filed: 02/05/2009
• Issued: 02/28/2012
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, June-mo, Kim, Suk-pil, Yoon, Tae-Eung
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Nicely, Joseph C
• Application Number:
  US12/366,151
• Publication Number:
  US 20090321878A1
• Time in Patent Office: 1,118 Days
• Field of Search: 365/148, 365/163, 257/2, 257/4, 257/5, 257/42, 257/467, 257/537, 257/E45.002, 257/E45.003, 257/E33.046, 257/E29.17, 257/E29.079, 257/E29.08, 257/E29.326, 257/E21.004, 438/54, 438/102, 438/103, 438/382, 438/385
• US Class Current: 257/42
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

Claims

1. A non-volatile memory device comprising:

at least one first electrode;

at least one second electrode crossing the at least one first electrode;

at least one data storing layer interposed between the at least one first electrode and the at least one second electrode, at a region in which the at least one first electrode crosses the at least one second electrode;

at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at a region in which the at least one first electrode crosses the at least one second electrode; and

at least one junction layer interposed between the at least one first electrode and the at least one metal silicide layer, and the at least one first electrode comprises a first semiconductor having a first conductivity, and the at least one junction layer comprises a second semiconductor having a second conductivity which is opposite to the first conductivity, wherein the at least one junction layer is recessed in a sidewall of the at least one first electrode.

2. The non-volatile memory device of claim 1, wherein the at least one metal silicide layer is interposed between the at least one first electrode and the at least one data storing layer.

3. The non-volatile memory device of claim 1, wherein the at least one metal silicide layer is interposed between the at least one junction layer and the at least one second electrode.

4. The non-volatile memory device of claim 1, wherein the at least one second electrode comprises a metal.

5. The non-volatile memory device of claim 1, wherein the at least one first electrode and the at least one second electrode are arranged to cross each other at a right angle.

6. The non-volatile memory device of claim 1, wherein the data storing layer comprises a variable resistor.

7. A non-volatile memory device comprising:

a plurality of first electrodes, wherein the plurality of the first electrodes are stacked as a plurality of stacked layers;

a plurality of second electrodes disposed between and crossing the plurality of the first electrodes;

at least one data storing layer interposed between the plurality of first electrodes and the plurality of second electrodes, at a region in which the plurality of first electrodes cross the plurality of second electrodes; and

a plurality of metal silicide layers interposed between the plurality of first electrodes and the plurality of second electrodes, at a region in which the plurality of first electrodes cross the plurality of second electrodes,

wherein the at least one data storing layer extends along the plurality of the first electrodes constituting the plurality of stacked layers.