Implementation of diffusion barrier in 3D memory
First Claim
Patent Images
1. A memory cell, comprising:
- a first conductor in a trench in a first dielectric, the first dielectric over and interfacing with a semiconductor substrate, the trench in the first dielectric not formed all the way through to the semiconductor substrate such that a portion of the first dielectric remains between the first conductor and the substrate;
a second conductor in a trench in a second dielectric; and
a non-silicided pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, the pillar comprising;
a non-silicided semiconductor over the first conductor; and
a non-silicided antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell, a top surface of the antifuse that faces the second conductor not extending above a bottom surface of the second dielectric such that a bottom surface of the second conductor that faces the pillar is substantially uniform in the trench in the second dielectric,at least one of a portion of the trench in the first dielectric layer and a portion of the trench in the second dielectric layer not occupied by the first conductor and the second conductor, respectively, filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier but not the first conductor or the second conductor.
4 Assignments
0 Petitions
Accused Products
Abstract
One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
26 Citations
26 Claims
-
1. A memory cell, comprising:
-
a first conductor in a trench in a first dielectric, the first dielectric over and interfacing with a semiconductor substrate, the trench in the first dielectric not formed all the way through to the semiconductor substrate such that a portion of the first dielectric remains between the first conductor and the substrate; a second conductor in a trench in a second dielectric; and a non-silicided pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, the pillar comprising; a non-silicided semiconductor over the first conductor; and a non-silicided antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell, a top surface of the antifuse that faces the second conductor not extending above a bottom surface of the second dielectric such that a bottom surface of the second conductor that faces the pillar is substantially uniform in the trench in the second dielectric, at least one of a portion of the trench in the first dielectric layer and a portion of the trench in the second dielectric layer not occupied by the first conductor and the second conductor, respectively, filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier but not the first conductor or the second conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A memory cell, comprising:
-
a first conductor; a first diffusion barrier over and interfacing with the first conductor; a non-silicided pillar over and interfacing with the first diffusion barrier, but the non-silicided pillar not interfacing with the first conductor; a second diffusion barrier over and interfacing with the non-silicided pillar; a second conductor over and interfacing with the second diffusion barrier, but the second conductor not interfacing with the pillar; and a third diffusion barrier over and interfacing with the second conductor, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, the first conductor in a trench in a first dielectric, the first dielectric over and interfacing with a semiconductor substrate, the trench in the first dielectric not formed all the way through to the semiconductor substrate such that a portion of the first dielectric remains between the first conductor and the substrate, the second conductor in a trench in a second dielectric, at least one of a portion of the trench in the first dielectric layer and a portion of the trench in the second dielectric layer not occupied by the first conductor and the second conductor, respectively, is filled with the first and third diffusion barriers, respectively, and the non-silicided pillar comprising; a non-silicided semiconductor; and a non-silicided antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell, a top surface of the antifuse that faces the second conductor not extending above a bottom surface of the second dielectric such that a bottom surface of the second conductor that faces the pillar is substantially uniform in the trench in the second dielectric. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A memory cell, comprising:
-
a first copper conductor; a non-silicided pillar over the first conductor; and a second copper conductor over the pillar, the pillar comprising; a non-silicided semiconductor over the first conductor; and a non-silicided antifuse over the semiconductor; the non-silicided antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell, the first copper conductor in a trench in a first dielectric over and interfacing with a semiconductor substrate, the trench in the first dielectric not formed all the way through to the semiconductor substrate, and a portion of the trench filled with a first diffusion barrier flush with a top surface of the first dielectric such that the pillar interfaces with the first diffusion barrier but the pillar does not interface with the first copper conductor, and the second conductor in a trench in a second dielectric, the trench in the second dielectric lined with a second diffusion barrier, a top surface of the non-silicided pillar that faces the second conductor being substantially flush with a bottom surface of the second dielectric such that the second diffusion barrier has a substantially uniform thickness in the bottom of the trench in the second dielectric. - View Dependent Claims (18, 19, 20, 21, 22, 23)
-
-
24. A memory cell, comprising:
-
a substantially U shaped first diffusion barrier lining a first trench in a first dielectric layer over a substrate, the first trench not formed all the way through the first dielectric layer to the substrate such that a portion of the first dielectric remains between the first diffusion barrier and the substrate; a substantially U shaped second diffusion barrier over the first diffusion barrier in the first trench; a first conductor over the second diffusion barrier in the first trench; a third diffusion barrier over the first conductor in the first trench, such that the first conductor is encircled by the second diffusion barrier and the third diffusion barrier; a fourth diffusion barrier over the third diffusion barrier, topmost surfaces of the first diffusion barrier, the second diffusion barrier and the fourth diffusion barrier that face away from the substrate being substantially flush with a topmost surface of the first dielectric that faces away from the substrate; a non-silicided pillar comprising; a non-silicided semiconductor over the first conductor, a bottom surface of the non-silicided semiconductor that faces toward the substrate in contact with the topmost surfaces of the first, second and fourth diffusion barriers, but not in contact with the first conductor; a non-silicided antifuse over the non-silicided semiconductor, the non-silicided antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell; a fifth diffusion barrier over the non-silicided antifuse; and a hardmask over the fifth diffusion barrier; a substantially U shaped sixth diffusion barrier lining a second trench in a second dielectric layer overlying the non-silicided pillar; a substantially U shaped seventh diffusion barrier over the sixth diffusion barrier in the second trench; a second conductor over the seventh diffusion barrier in the second trench; an eighth diffusion barrier over the second conductor in the second trench, such that the second conductor is encircled by the seventh diffusion barrier and the eighth diffusion barrier; and a ninth diffusion barrier over the eighth diffusion barrier. - View Dependent Claims (25, 26)
-
Specification