Thin film transistor

• US 8,124,972 B2
• Filed: 04/24/2009
• Issued: 02/28/2012
• Est. Priority Date: 04/25/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Dairiki, Koji, Miyairi, Hidekazu, Isa, Toshiyuki, Miyanaga, Akiharu, Yamazaki, Shunpei, Hirohashi, Takuya, Watabe, Takeyoshi
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US12/429,486
• Publication Number:
  US 20090267068A1
• Time in Patent Office: 1,040 Days
• Field of Search: 257/57, 257/59, 257/66, 257/E29.291, 257/E29.273, 257/E21.412, 257/E21.413, 257/56, 257/72, 257/E21.142, 257/E21.143
• US Class Current: 257/57
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.

Claims

1. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the substrate, the gate insulating layer covering the gate electrode;

a first semiconductor layer over and in contact with the gate insulating layer, the first semiconductor layer including a plurality of crystal regions included in an amorphous structure;

at least two second semiconductor layers for forming a source region and a drain region, the at least two second semiconductor layers including an impurity element imparting one conductivity type; and

a buffer layer formed using an amorphous semiconductor between the first semiconductor layer and the at least two second semiconductor layers,

wherein the plurality of the crystal regions includes an inverted conical or inverted pyramidal crystal grain which grows substantially radially in a direction in which the first semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the first semiconductor layer, and

wherein the first semiconductor layer includes a crystal grain with a size of greater than or equal to 1 nm and less than or equal to 5 nm.

2. The thin film transistor according to claim 1, wherein the first semiconductor layer has an NH group.

3. The thin film transistor according to claim 1, wherein a nitrogen concentration of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is 1×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.

4. The thin film transistor according to claim 1, wherein a nitrogen concentration of a portion of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is 3×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>,

wherein the portion is in a vicinity of the interface between the gate insulating layer and the first semiconductor layer, and

wherein the nitrogen concentration is reduced in a thickness direction of the first semiconductor layer from the vicinity of the interface.

5. The thin film transistor according to claim 1, wherein a peak region of a spectrum of the first semiconductor layer, which is measured by low-temperature photoluminescence spectroscopy, is greater than or equal to 1.31 eV and less than or equal to 1.39 eV.

6. The thin film transistor according to claim 1, wherein an oxygen concentration of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup>.

7. The thin film transistor according to claim 1, wherein each of the plurality of crystal regions is a single crystal.

8. The thin film transistor according to claim 1, wherein the plurality of the crystal regions includes a twin crystal.

9. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the substrate, the gate insulating layer covering the gate electrode;

a first semiconductor layer over and in contact with the gate insulating layer, the first semiconductor layer including a plurality of crystal regions included in an amorphous structure;

a second semiconductor layer having an amorphous structure over the first semiconductor layer; and

at least two third semiconductor layers for forming a source region and a drain region, the at least two third semiconductor layers including an impurity element imparting one conductivity type,

wherein the plurality of the crystal regions includes an inverted conical or inverted pyramidal crystal grain which grows substantially radially in a direction to the second semiconductor layer from a position away from an interface between the gate insulating layer and the first semiconductor layer, and

wherein the first semiconductor layer includes a crystal grain with a size of greater than or equal to 1 nm and less than or equal to 5 nm.

10. The thin film transistor according to claim 9, wherein the first semiconductor layer has an NH group.

11. The thin film transistor according to claim 9, wherein an oxygen concentration of the first semiconductor layer measured by secondary ion mass spectrometry is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup>, and

wherein a nitrogen concentration of the first semiconductor layer measured by secondary ion mass spectrometry is 1×

10¹⁹ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.

12. The thin film transistor according to claim 9, wherein a nitrogen concentration of a portion of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is 3×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>,

wherein the portion is in a vicinity of the interface between the gate insulating layer and the first semiconductor layer, and

wherein the nitrogen concentration is reduced in a thickness direction of the first semiconductor layer from the vicinity of the interface.

13. The thin film transistor according to claim 9, wherein a peak region of a spectrum of the first semiconductor layer, which is measured by low-temperature photoluminescence spectroscopy, is greater than or equal to 1.31 eV and less than or equal to 1.39 eV.

14. The thin film transistor according to claim 9, wherein an oxygen concentration of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup>.

15. The thin film transistor according to claim 9, wherein each of the plurality of the crystal regions is a single crystal.

16. The thin film transistor according to claim 9, wherein the plurality of the crystal regions includes a twin crystal.

17. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the gate electrode;

a first semiconductor layer over and in contact with the gate insulating layer, the first semiconductor layer including a plurality of crystal regions included in an amorphous structure;

a second semiconductor layer having an amorphous structure over the first semiconductor layer; and

a source region and a drain region over the second semiconductor layer,

wherein the source region and the drain region include an impurity element imparting one conductivity type,

wherein the plurality of the crystal regions includes an inverted conical or inverted pyramidal crystal grain, in which a vertex of the inverted conical or the inverted pyramidal crystal grain is closer to an interface between the gate insulating layer and the first semiconductor layer than the second semiconductor layer, and

wherein the first semiconductor layer includes a crystal grain with a size of greater than or equal to 1 nm and less than or equal to 5 nm.

18. The thin film transistor according to claim 17, wherein the first semiconductor layer has an NH group.

19. The thin film transistor according to claim 17, wherein an oxygen concentration of the first semiconductor layer measured by secondary ion mass spectrometry is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup>, and

wherein a nitrogen concentration of the first semiconductor layer measured by secondary ion mass spectrometry is 1×

10¹⁹ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.

20. The thin film transistor according to claim 17, wherein a nitrogen concentration of a portion of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is 3×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>,

wherein the portion is in a vicinity of the interface between the gate insulating layer and the first semiconductor layer, and

wherein the nitrogen concentration is reduced in a thickness direction of the first semiconductor layer from the vicinity of the interface.

21. The thin film transistor according to claim 17, wherein a peak region of a spectrum of the first semiconductor layer, which is measured by low-temperature photoluminescence spectroscopy, is greater than or equal to 1.31 eV and less than or equal to 1.39 eV.

22. The thin film transistor according to claim 17, wherein an oxygen concentration of the first semiconductor layer, which is measured by secondary ion mass spectrometry, is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup>.

23. The thin film transistor according to claim 17, wherein each of the plurality of the crystal regions is a single crystal.

24. The thin film transistor according to claim 17, wherein the plurality of the crystal regions includes a twin crystal.