Trench MOSgated device with deep trench between gate trenches

• US 8,125,024 B2
• Filed: 03/03/2008
• Issued: 02/28/2012
• Est. Priority Date: 03/01/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Boden, Milton J.
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/041,017
• Publication Number:
  US 20080211016A1
• Time in Patent Office: 1,457 Days
• Field of Search: None
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and boron doped polysilicon which is connected to the source electrode fills the trench. The structure has reduced capacitance and improved resistance to single event rupture and single event breakdown and improved resistance to parasitic bipolar action.

Claims

1. A trench MOSFET structure comprising a plurality of parallel spaced gate trenches extending through a source region of a first conductivity type, an underlying channel region of the opposite conductivity type and into a drift region of the first conductivity type;

and a deep trench having a depth deeper than said gate trenches and disposed between each pair of said gate trenches;

each of said deep trenches including sidewalls that receive an implant of said opposite conductivity type and a bottom surface that does not receive said implant, said deep trenches being filled with a conductive polysilicon of said opposite conductivity type; and

a top contact connected to said source region and said conductive polysilicon in said deep trenches.

2. The device of claim 1, wherein said deep trenches have an insulation mass beneath said conductive polysilicon therein.

3. The device of claim 2, wherein said insulation mass comprises an oxide.

4. The device of claim 1, wherein said conductive polysilicon is, boron doped.

5. The device of claim 1, wherein said first conductivity type is N type, and said opposite conductivity type is P type.

6. The device of claim 1, wherein said drift region is grown epitaxially over a body.

7. A trench device structure comprising a plurality of parallel spaced gate trenches extending through a source region of a first conductivity type, an underlying channel region of the opposite conductivity type and into a drift region of the first conductivity type, said drift region grown epitaxially over a body;

and a deep trench having a depth deeper than said gate trenches and disposed between each pair of said gate tranches;

each of said deep trenches including sidewalls that receive an implant of said opposite conductivity type and a bottom surface that does not receive said implant, said deep trenches being filled with a conductive polysilicon of said opposite conductivity type; and

a top contact connected to said source region and said conductive polysilicon in said deep trenches.

8. The device of claim 7, wherein said body comprises an N type body to configure the device as a MOSFET.

9. The device of claim 7, wherein said body comprises a buffer layer and a P type region to configure the device as an IGBT.

10. The device of claim 7, wherein said deep trenches have an insulation mass beneath said conductive polysilicon therein.