Gate of trench type MOSFET device and method for forming the gate

• US 8,125,026 B2
• Filed: 11/13/2009
• Issued: 02/28/2012
• Est. Priority Date: 12/09/2008
• Status: Expired due to Fees

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Jung, Ji-Houn
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US12/617,810
• Publication Number:
  US 20100140690A1
• Time in Patent Office: 837 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/E29.257, 257/E29.26, 257/E29.262, 257/E21.41, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence

Abstract

A gate of a trench type MOSFET device and a method of forming a gate. A gate of a trench type MOSFET device may include a gate oxide film formed on and/or over a trench type gate poly such that parasitic capacitance may be produced in a gate poly. An electric field may be substantially uniformly formed in a MESA region surrounding a gate poly. An overcurrent may be substantially prevented from flowing into a MOS channel around a gate. A gate oxide film may be substantially prevented from being destroyed and/or leakage may be substantially prevented. Reliability of a device may be maximized.

Claims

1. An apparatus comprising:

a first gate oxide film formed over a trench region;

a first polysilicon film deposited over said first gate oxide film to have a predetermined thickness;

a second gate oxide film deposited over said first polysilicon film; and

a second polysilicon film over said second gate oxide film,

wherein said predetermined thickness of said first polysilicon film is between approximately 500 Å and

1000 Å

.

2. The apparatus of claim 1, wherein:

said first oxide film is formed at least over a portion of an inner wall of said trench region; and

said second polysilicon film gap-fills said trench region.

3. The apparatus claim 1, wherein parasitic capacitance is produced between said first gate oxide film and said second gate oxide film.

4. The apparatus of claim 1, wherein at least one of:

an electric field is substantially uniformly formed in a MESA region surrounding a gate poly; and

an overcurrent is substantially prevented from flowing into a MOS channel around a gate.

5. The apparatus of claim 1, comprising a trench type MOSFET device.

6. The apparatus of claim 5, wherein a gate is buried in said trench region.

7. The apparatus of claim 1, comprising an insulating film over a least a portion of a semiconductor substrate in which said trench region is formed.

8. A method comprising:

forming a first gate oxide film over a trench region;

forming a first polysilicon film over a surface of a semiconductor substrate in which the trench region is formed and the first gate oxide film;

forming a photoresist mask over said first polysilicon film exposing the first polysilicon film over said trench region;

etching said first polysilicon film using said photoresist mask such that said first polysilicon film remains having a predetermined thickness over said trench region;

forming a second gate oxide film over first polysilicon film-said over said trench region; and

forming a second polysilicon film over the second gate oxide film,

wherein said predetermined thickness of said first polysilicon film is between approximately 500 Å and

1000 Å

.

9. The method of claim 8, wherein:

said first oxide film is formed at least over a portion of an inner wall of said trench region; and

said second polysilicon film gap-fills said trench region.

10. The method of claim 8, wherein at least one of said first polysilicon film and said second polysilicon film is formed over substantially the entire surface of said semiconductor substrate.

11. The method of claim 8, wherein forming said second polysilicon film comprises an etch back process.

12. The method of claim 8, wherein forming said photoresist mask comprises:

applying a photoresist film over the surface of said semiconductor substrate over which said first polysilicon film is formed; and

patterning said photoresist film such that said trench region is exposed.

13. The method of claim 12, wherein said photoresist film is applied to substantially the entire surface of said semiconductor substrate.

14. The method of claim 8, wherein parasitic capacitance is produced between said first gate oxide film and said second gate oxide film.

15. The method of claim 8, wherein at least one of:

an electric field is substantially uniformly formed in a MESA region surrounding a gate poly; and

an overcurrent is substantially prevented from flowing into a MOS channel around a gate.

16. The method of claim 8, comprising forming a trench type MOSFET device.

17. The method of claim 16, comprising forming a gate buried in said trench region.

18. The method of claim 8, comprising forming an insulating film over a least a portion of said semiconductor substrate.