Increased I/O semiconductor package and method of making same

• US 8,125,064 B1
• Filed: 07/28/2008
• Issued: 02/28/2012
• Est. Priority Date: 07/28/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Lee, Chang Deok, Na, Do Hyun
• Primary Examiner(s): Chu, Chris
• Application Number:
  US12/181,256
• Time in Patent Office: 1,310 Days
• Field of Search: 257/E23.006, 257/E23.065, 257/684, 257/698, 257/699, 257/700, 257/701, 257/708, 257/729, 257/730, 257/738, 257/787, 257/790, 257/E23.067, 438/106, 438/121, 438/127, 438/667, 438/758
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.

Claims

1. A semiconductor package, comprising:

a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer and an insulation layer formed on at least a portion of the patterned metal layer, the substrate defining a plurality of holes which are segregated into at least four sets, the holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;

a plurality of lands disposed within respective ones of the holes of the substrate;

at least one semiconductor die mounted to the substrate;

at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; and

an encapsulant covering at least the semiconductor die and the electrical coupling member.

2. The semiconductor package of claim 1, wherein the patterned metal layer is made of a metal alloy including at least one metal selected from the group consisting of copper, aluminum, and nickel.

3. The semiconductor package of claim 1, wherein the holes in the patterned metal layer are each internally coated by the insulation layer.

4. The semiconductor package of claim 1, wherein the insulation layer is made of an insulation resin.

5. The semiconductor package of claim 1, wherein each of the lands completely fills a corresponding one of the holes of the substrate.

6. The semiconductor package of claim 1, wherein the substrate further includes at least one penetration opening formed therein.

7. The semiconductor package of claim 6, the penetration opening is filled with the encapsulant.

8. The semiconductor package of claim 1, wherein the lands are arranged in a generally radial pattern which extends from the central die mounting area of the substrate.

9. The semiconductor package of claim 1, wherein the substrate is provided with at least one step so as to define an inner portion which is of a first thickness, a middle portion which circumvents the inner portion and is of a second thickness exceeding the first thickness, and a peripheral outer portion which circumvents the middle portion and is of a third thickness exceeding the second thickness.

10. The semiconductor package of claim 9, wherein the lands are segregated into multiple sets which are of differing heights and disposed within respective ones of the inner, middle and outer portions of the substrate.

11. The semiconductor package of claim 10, wherein the at least one semiconductor die comprises a plurality of stacked semiconductor dies mounted to the inner portion of the substrate and electrically connected to at least one of the lands of each of the sets thereof.

12. The semiconductor package of claim 1, wherein the substrate defines a peripheral portion of reduced thickness.

13. The semiconductor package of claim 12, wherein at least one lead is connected to the peripheral portion of the substrate, the lead protruding from the encapsulant.

14. The semiconductor package of claim 13, wherein the encapsulant covers a portion of the lead and effectively fixes the lead to the substrate.

15. The semiconductor package of claim 1, wherein a solder ball is electrically connected to each of the lands.

16. The semiconductor package of claim 1, further comprising:

a rerouting film disposed on the substrate and electrically connected to the lands by an internal electrical path;

the semiconductor die being mounted to the rerouting film, with at least some of the lands being located beneath the semiconductor die, the electrical coupling member electrically connecting the semiconductor die to the rerouting film, and the encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the rerouting film.

17. A semiconductor package, comprising:

a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer and an insulation layer formed on at least a portion of the patterned metal layer, the patterned metal layer including a plurality of holes which are each internally coated by the insulation layer to collectively define a plurality of insulated holes in the substrate which are segregated into at least four sets, the insulated holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the insulated holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;

a plurality of lands disposed within respective ones of the insulated holes of the substrate;

at least one semiconductor die mounted to the substrate;

at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; and

an encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the substrate.

18. The semiconductor package of claim 17, wherein each of the lands defines opposed ends which are exposed in and substantially flush with the insulation layer.

19. The semiconductor package of claim 17, wherein a solder ball is electrically connected to each of the lands.

20. A semiconductor package, comprising:

a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer including a plurality of holes formed therein, and an insulation layer which encapsulates the patterned metal layer and internally coats each of the holes thereof such that the patterned metal layer and the insulation layer collectively define a plurality of insulated holes in the substrate which are segregated into at least four sets, the insulated holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the insulated holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;

a plurality of lands disposed within respective ones of the insulated holes of the substrate;

at least one semiconductor die mounted to the substrate;

at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; and

an encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the substrate.