Wafer integrated with permanent carrier and method therefor

• US 8,125,073 B2
• Filed: 01/11/2011
• Issued: 02/28/2012
• Est. Priority Date: 03/25/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Han, Byung Joon, Suthiwongsunthorn, Nathapong, Marimuthu, Pandi Chelvam, Heng, Kock Liang
• Primary Examiner(s): Ghyka, Alexander
• Assistant Examiner(s): ABDELAZIEZ, YASSER A
• Application Number:
  US13/004,111
• Publication Number:
  US 20110101509A1
• Time in Patent Office: 413 Days
• Field of Search: None
• US Class Current: 257/698
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.

Claims

1. A semiconductor device, comprising:

a wafer for supporting the semiconductor device;

a conductive layer formed over a top surface of the wafer;

a carrier wafer permanently bonded over the conductive layer; and

an interconnect structure formed within the wafer and the carrier wafer, wherein the interconnect structure includes,

a first via formed in the wafer that exposes the conductive layer,

a second via formed in the carrier wafer that exposes the conductive layer,

a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and

a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer.

2. The semiconductor device of claim 1, further including first and second insulation layers deposited over the first and second metal layers respectively, the first or second insulation layer has an etched portion that exposes a portion of the first or second metal layer.

3. The semiconductor device of claim 2, further including:

a semiconductor package connected over the etched portion of the first or second insulation layer; and

underfill material deposited between the semiconductor package and the etched portion of the first or second insulation layer.

4. The semiconductor device of claim 1, wherein the carrier wafer further includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic.

5. The semiconductor device of claim 1, wherein the carrier wafer is permanently bonded over an active surface of the wafer with an anodic bonding process.

6. The semiconductor device of claim 1, wherein the interconnect structure within the wafer and the carrier wafer is formed with a fabrication process that exceeds approximately 350°

C.

7. A semiconductor device, comprising:

a wafer for supporting the semiconductor device;

a conductive layer formed over a top surface of the wafer;

a carrier wafer permanently bonded over the conductive layer, the carrier wafer includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic; and

an interconnect structure formed within the wafer and the carrier wafer, the interconnect structure includes;

a first metal layer formed in the wafer and in electrical contact with the conductive layer, and

a second metal layer formed in the carrier wafer and in electrical contact with the conductive layer.

8. The semiconductor device of claim 7, further including:

a first via formed in the wafer, the first metal layer formed in the first via and in electrical contact with the conductive layer; and

a second via formed in the carrier wafer, the second metal layer formed in the second via and in electrical contact with the conductive layer.

9. The semiconductor device of claim 7, further including first and second insulation layers deposited over the first and second metal layers respectively, the first or second insulation layer has an etched portion that exposes a portion of the first or second metal layer.

10. The semiconductor device of claim 9, further including:

an under bump metallization layer formed over the etched portion of the first or second insulation layer; and

solder bumps formed over the under bump metallization layer.

11. The semiconductor device of claim 8, further including a semiconductor package connected to the first or second metal layer.

12. The semiconductor device of claim 8, wherein the interconnect structure is formed within the wafer at temperatures that exceed approximately 350°

C.

13. A semiconductor device, comprising:

a first substrate

a conductive layer formed over a surface of the first substrate;

a second substrate permanently bonded to the conductive layer and first substrate;

a first interconnect structure formed over and through the first substrate and electrically connected to the conductive layer;

a second interconnect structure formed over and through the second substrate and electrically connected to the conductive layer; and

a first insulation layer deposited over and into the first interconnect structure; and

a second insulation layer deposited over and into the second interconnect structure.

14. The semiconductor device of claim 13, wherein the first interconnect structure includes:

a first via formed through the first substrate to expose the conductive layer; and

a first metal layer formed over a surface of the first substrate and into the first via and electrically connected to the conductive layer.

15. The semiconductor device of claim 13, further including a semiconductor package mounted to the second interconnect structure.

16. The semiconductor device of claim 13, wherein the second substrate includes a material selected from the group consisting of glass, silicon, silicon carbide, and ceramic.

17. The semiconductor device of claim 13, wherein the second substrate is permanently bonded to the first substrate with an anodic bonding process.

18. The semiconductor device of claim 13, wherein the first interconnect structure is formed over and through the first substrate and the second interconnect structure is formed over and through the second substrate at a temperature in excess of approximately 350°

C.

19. The semiconductor device of claim 13, wherein the second interconnect structure includes:

a second via formed through the second substrate to expose the conductive layer; and

a second metal layer formed over a surface of the second substrate and into the second via and electrically connected to the conductive layer.

20. A method of making a semiconductor device, comprising:

providing a first substrate;

forming a first conductive layer over the first substrate;

mounting a second substrate to the first conductive layer and first substrate;

forming a first via through the first substrate to expose the first conductive layer;

conformally applying a first insulating layer over a surface of the first substrate and into the first via;

conformally applying a second conductive layer over the first insulating layer and into the first via and electrically connected to the first conductive layer;

forming a second via through the second substrate to expose the first conductive layer;

conformally applying a third conductive layer over a surface of the second substrate and into the second via and electrically connected to the first conductive layer;

forming a second insulating layer over the second conductive layer and into the first via; and

forming a third insulating layer over the third conductive layer and into the second via.

21. The method of claim 20, including mounting a semiconductor package over the second substrate.

22. The method of claim 21, including depositing an underfill material between the semiconductor package and the second substrate.

23. The method of claim 21, including forming a shield over the semiconductor package.

24. The method of claim 21, including forming a heat sink over the semiconductor package.

25. The method of claim 20, including forming a plurality of bumps over the first conductive layer.

26. The method of claim 20, including forming a fourth insulating layer between the first substrate and second substrate.

27. A method of making a semiconductor device, comprising:

providing a first substrate;

forming a first conductive layer over the first substrate;

mounting a second substrate to the first conductive layer and first substrate;

forming a first via through the first substrate to expose the first conductive layer;

forming a second conductive layer over a surface of the first substrate and into the first via and electrically connected to the first conductive layer;

forming a second via through the second substrate to expose the first conductive layer;

forming a third conductive layer over a surface of the second substrate and into the second via and electrically connected to the first conductive layer;

forming a first insulating layer over the second conductive layer and into the first via; and

forming a second insulating layer over the third conductive layer and into the second via.

28. The method of claim 27, including mounting a semiconductor package over the second substrate.

29. The method of claim 28, including depositing an underfill material between the semiconductor package and the second substrate.

30. The method of claim 28, including forming a shield over the semiconductor package.

31. The method of claim 28, including forming a heat sink over the semiconductor package.

32. The method of claim 27, including forming a plurality of bumps over the first conductive layer.

33. The method of claim 27, including forming a third insulating layer between the first substrate and second substrate.