Integrity checking of configurable data of programmable device

• US 8,125,243 B1
• Filed: 09/28/2007
• Issued: 02/28/2012
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/904,643
• Time in Patent Office: 1,614 Days
• Field of Search: 326 37- 41, 326/47, 716/16, 365/189.05, 365/189.11
• US Class Current: 326/41
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and a system for continuous integrity checking of configuration data of programmable device are disclosed. In one embodiment, a method includes performing a redundancy check (RC) of configuration data loaded to configuration registers to produce a master RC data. The method further includes iteratively comparing a current RC data obtained by performing the redundancy check (RC) of current configuration data of the configuration registers with the master RC data until there is a mismatch between the current RC data and the master RC data. Additionally, the method includes performing an exception event in response to the mismatch.

Claims

1. A method of operating a programmable device, comprising:

(a) accessing a master summary data and loading an original configuration data to configuration registers of the programmable device;

(b) generating a current summary data by performing a summary operation of a current configuration data of the configuration registers of the programmable device;

(c) comparing the current summary data with the master summary data;

(d) performing an exception action if the current summary data does not match with the master summary data;

(e) repeating the (b), (c), and (d) continuously; and

storing at least one duplicate of the master summary data to a dedicated memory location.

2. The method of claim 1, wherein the programmable device comprises at least one of:

a programmable system on chip (PSoC); and

a field programmable gate array (FPGA) with an embedded processor.

3. The method of claim 1, wherein the accessing the master summary data comprises at least one of:

reading the master summary data provided to the programmable device; and

calculating the master summary data based on the original configuration data loaded into the configuration registers.

4. The method of claim 3, wherein the master summary data is generated by performing a cyclic redundancy check (CRC) of the original configuration data.

5. The method of claim 1, wherein the generating the current summary data is controlled by a direct memory access (DMA) controller.

6. The method of claim 1, wherein the performing the summary operation comprises performing a cyclic redundancy check (CRC) of the current configuration data to obtain the current summary data.

7. The method of claim 1, wherein the performing the exception action comprises communicating an interrupt signal to a processor of the programmable device.

8. The method of claim 7, wherein the performing the exception action further comprises reloading the configuration registers with original configuration data.

9. The method of claim 1, further comprising comparing the master summary data with the at least one duplicate of the master summary data to check an integrity of the master summary data.

10. A method of operating a programmable device, comprising:

loading an original configuration data to configuration registers of the programmable device;

performing a redundancy check (RC) of the original configuration data to produce a master RC data;

iteratively comparing a current RC data obtained by performing the redundancy check (RC) of a current configuration data of the configuration registers with the master RC data until there is a mismatch between the current RC data and the master RC data; and

storing at least one duplicated of the master RC data in a dedicated memory location.

11. The method of claim 10, further comprising communicating an interrupt data to a processor of the programmable device when the current RC data does not match with the master RC data.

12. The method of claim 10, further comprising reloading the configuration registers with the original configuration data when the current RC data does not match with the master RC data.

13. The method of claim 10, wherein the redundancy check includes at least one of:

a checksum;

a cyclic redundancy check;

a horizontal redundancy check;

a vertical redundancy check; and

a cryptographic message digest.

14. The method of claim 10, wherein the redundancy check (RC) of the original configuration data or the current configuration data is performed using a direct access memory (DMA) controller.

15. A system of operating a programmable device, comprising:

a first memory to store a master summary data obtained through performing a summary operation of an original configuration data initially loaded to configuration registers of the programmable device;

a second memory to store a current summary data obtained through performing a summary operation of current configuration data of the configuration registers;

a comparator module to compare the current summary data and the master summary data and to generate an exception signal when the current summary data does not match with the master summary data; and

an auxiliary memory at least one duplicate of the master summary data at a dedicated memory location.

16. The system of claim 15, further comprising a direct memory access (DMA) controller coupled to the first memory and the second memory to access the master summary data and the current summary data.

17. The system of claim 15, wherein the summary operation is a cyclic redundancy check (CRC).

18. The system of claim 16, further comprising a processor to process the exception signal.