AM chirp LADAR readout circuit and module

• US 8,125,367 B2
• Filed: 07/15/2010
• Issued: 02/28/2012
• Est. Priority Date: 08/06/2009
• Status: Active Grant

• Current Assignee: PFG Ip, LLC
• Original Assignee: Irvine Sensors Corp.
• Inventors: Ludwig, David
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/804,267
• Publication Number:
  US 20110032130A1
• Time in Patent Office: 593 Days
• Field of Search: 341/122, 341/155, 356/5.09, 356/5.01
• US Class Current: 341/155
• CPC Class Codes: G01S 17/89 for mapping or imaging
• CPC Class Codes: G01S 7/4913 Circuits for detection, sampling, integration or read-out
• CPC Class Codes: H03M 1/1215 using time-division multiplexing

Abstract

A readout circuit which may be in the form of a readout integrated circuit or ROIC is disclosed for use in an AM chirp LADAR system having a photodetector coupled to a passive electronic filter. The filter output is coupled to a capacitive-coupled transimpedance amplifier with an output coupled to an analog storage register. The analog storage register output is coupled to a sample-and-hold circuit which in turn is coupled to an analog to digital converter circuit. In the stacked configuration, each IC operates independently and outputs its signals on a unique output line. The stacked ICs operate under the same set of control vectors as the individual ICs comprising the stack.

Claims

1. An electronic circuit comprising:

a filter circuit having a filter input and a filter output,

the filter output coupled to a capacitive-coupled transimpedance amplifier,

the capacitive-coupled transimpedance amplifier coupled to an analog storage register,

the analog storage register coupled to a sample-and-hold circuit,

the sample and hold circuit coupled to an analog-to-digital converter circuit.

2. The circuit of claim 1 wherein the filter input is coupled to a detector circuit.

3. The circuit of claim 2 wherein the detector circuit is a metal-semiconductor-metal detector circuit having a detector bias.

4. The circuit of claim 3 wherein the detector bias is modulated by a predetermined frequency.

5. A device comprised of a plurality of electronic circuits, wherein at least two of the electronic circuits comprise:

a filter circuit having a filter input and a filter output,

the filter input coupled to a capacitive-coupled transimpedance amplifier,

the output of the capacitive-coupled transimpedance amplifier coupled to an analog storage register,

wherein at least two of outputs of the plurality of analog storage registers are coupled to a multiplexer circuit,

the output of the multiplexer circuit is coupled to a sample-and-hold circuit and the sample and hold circuit is coupled to an analog-to-digital circuit.

6. The device of claim 5 wherein the filter input is coupled to a detector circuit.

7. The device of claim 6 wherein the detector circuit is a metal-semiconductor-metal detector circuit.

8. The device of claim 7 wherein the detector bias is modulated by a predetermined frequency.

9. The device of claim 5 wherein at least two of the electronic circuits comprise two integrated circuit chips.

10. The device of claim 9 wherein the at least two integrated circuit chips are bonded and stacked to define a microelectronic module.