Electro-luminescence display device

• US 8,125,473 B2
• Filed: 04/24/2009
• Issued: 02/28/2012
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Chung, Hoon Ju, Jeon, Chang Hoon
• Primary Examiner(s): Nguyen, Kevin M
• Application Number:
  US12/385,971
• Publication Number:
  US 20090207107A1
• Time in Patent Office: 1,040 Days
• Field of Search: 345/207, 345/76, 345/77, 345/82, 345/83
• US Class Current: 345/207
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2360/144 the light being ambient light
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2029 the sub-frames having non-binary weights
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

An electro-luminescence display device and a method of driving the same for controlling a full white brightness depending upon a brightness of the external environment and thus controlling a brightness mode is disclosed. An electro-luminescence display device according to the present invention comprising: a display panel having pixels light-emitted by a supplied current; a data driver for applying a data voltage corresponding to said current to the pixels; and a timing controller for dividing one frame into a plurality of sub-frames and applying said data voltage corresponding to each of the plurality of sub-frames to the data driver and for controlling an emission time of each frame.

Claims

1. A flat panel display device, comprising:

a display panel having a plurality of pixels;

a photo sensor detecting a brightness of the external environment of the display panel;

a timing controller receiving N-bit video signals (wherein N is an integer) and the detected brightness and dividing one frame into a plurality of sub-frames, the timing controller modulating the N-bit video signals in response to the detected brightness and the number of the sub-frames; and

a data driver receiving the modulated N-bit video signals from the timing controller and applying data voltages corresponding to the modulated N-bit video signals to the pixels,

wherein the timing controller includes;

a selection signal generator for generating a selection signal in response to the detected brightness from the photo sensor;

a first data converter for converting the N-bit video signals (wherein N is an integer) into a first M-bit data (wherein M is an integer larger than N);

a second data converter for converting the N-bit video signals into a second M-bit data wherein a number of gray levels of the second M-bit data are less than that of the first M-bit data; and

a selector for selectively applying the N-bit video signals to any one of the first and second converters in response to the selection signal.

2. The flat panel display device according to claim 1, wherein the modulated N-bit video signals have an information on a turn-on time of the pixels during each sub-frame.

3. The flat panel display device according to claim 1, wherein the flat panel display device is an electro-luminescence display device.

4. The flat panel display device according to claim 1, wherein

the second converter sets M-K bits in the most significant bits of the M-bit data are set to ‘

0’

(wherein K is an integer smaller than M).

5. The flat panel display device according to claim 4, wherein the selection signal generator generates a first logical state of selection signal when the brightness of the external environment of the display panel is relatively high while generating a second logical state of selection signal when the brightness of the external environment of the display panel is relatively low.

6. The flat panel display device according to claim 5, wherein the selection signal generator applies the N-bit video signals to the first data converter in response to the first logical state of selection signal while applying the N-bit video signals to the second data converter in response to the second logical state of selection signal.

7. The flat panel display device according to claim 4, wherein each of the first and second data converters converts the N-bit video signals into the first or second M-bit data in such a manner to have any one of a binary code and a non-binary code.

8. The flat panel display device according to claim 7, wherein a gray level value corresponding to the first M-bit data converted by the first data converter is larger than a gray level value corresponding to the second M-bit data converted by the second data converter.

9. The flat panel display device according to claim 4, wherein each of the plurality of sub-frames has a light-emission time corresponding to each bit of the first or second M-bit data.

10. The flat panel display device according to claim 1, further comprising a gate driver for sequentially driving the pixels.

11. The flat panel display device according to claim 10, wherein the timing controller includes:

a control signal generator for applying a gate control signal to the gate driver in response to the selection signal.

12. The flat panel display device according to claim 11, wherein the control signal generator applies a gate control signal to reduce a turn-on time of the pixels during each sub-frame in response to the second logical state of the selection signal.

13. The flat panel display device according to claim 12, wherein the control signal generator reduces the turn-on time of the pixels during each sub-frame by having the gate driver apply an erasure pulse to the pixels.

14. The flat panel display device according to claim 13, wherein the reduced turn-on time of the pixels during each sub-frame is reduced at a ratio of J (wherein J is an integer) in comparison with a turn-on time of the pixels when the first logical state of the selection signal is applied to the gate driver.

15. The flat panel display device according to claim 4, wherein M is 12 and N is 6.