Correcting for phase noise of an oscillator

• US 8,126,420 B2
• Filed: 12/27/2007
• Issued: 02/28/2012
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Koroglu, Mustafa H., Tuttle, G. Tyson, Vancorenland, Peter J., Piovaccari, Alessandro
• Primary Examiner(s): LE, THANH C
• Application Number:
  US12/005,513
• Publication Number:
  US 20090170463A1
• Time in Patent Office: 1,524 Days
• Field of Search: 455/130, 455/255, 455/256, 455/259, 455/260, 455/295, 455/296, 455/307, 455/310, 455/311, 455/317, 455/318, 375/375, 375/376, 375/346
• US Class Current: 455/311
• CPC Class Codes: H04B 1/10 Means associated with receiver for limiting or suppressing noise or interference
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

In one embodiment, the present invention includes a method for digitizing a phase noise value indicative of a level of phase noise present in a LO signal and downconverting an RF signal to a second frequency signal using the LO signal. This downconversion can cause the phase noise to be transferred to the second frequency signal. The method may thus further include removing the phase noise from the second frequency signal using the digitized phase noise value.

Claims

1. An apparatus comprising:

a phase-to-digital converter (PDC) to receive a local oscillator (LO) signal and to determine a digital phase noise value corresponding to a measure of phase noise present in the LO signal, the PDC comprising;

a counter to receive the LO signal, the counter controlled by a reference clock, wherein the counter is to generate a count of LO signal cycles during a cycle of the reference clock;

a first storage coupled to the counter to store the count;

a delay line coupled to receive the LO signal, the delay line having L stages each to provide an output;

a second storage coupled to receive the L outputs and to provide a value of the L outputs responsive to the reference clock;

a decoder coupled to the second storage to receive the values and generate a decoder output corresponding to a number of partial LO cycles during the reference clock cycle; and

a first mixer to receive an intermediate frequency (IF) signal obtained from a received radio frequency (RF) signal and remove phase noise from the IF signal using the digital phase noise value.

2. The apparatus of claim 1, further comprising a second mixer to receive the RF signal and downconvert the RF signal to the IF signal using the LO signal, wherein the phase noise is transferred to the IF signal within the second mixer.

3. The apparatus of claim 2, further comprising a local oscillator to generate the LO signal, wherein the local oscillator does not include a phase lock loop.

4. The apparatus of claim 3, further comprising a feed forward loop coupled between the second mixer and the first mixer, the feed forward loop including the PDC.

5. The apparatus of claim 4, wherein the feed forward loop further comprises a low pass filter coupled to an output of the PDC to remove quantization noise generated by the PDC.

6. The apparatus of claim 1, wherein the PDC is to output a digital word including N+M bits, wherein the N bits correspond to the count and the M bits correspond to the decoder output.

7. The apparatus of claim 6, wherein the N bits are the most significant bits of the digital word and the M bits are the least significant bits of the digital word.

8. The apparatus of claim 1, wherein a beat frequency (f₀) of the PDC corresponds to a difference between a frequency of the LO signal and a product of the reference clock and a predetermined integer value less than the beat frequency, such that the PDC does not corrupt low frequency content.

9. A method comprising:

digitizing a phase noise value indicative of a level of phase noise present in a local oscillator (LO) signal, including generating a count of LO signal cycles during a cycle of a reference clock, storing the count, receiving the LO signal in a delay line, the delay line having L stages each to provide an output, providing a value of the L outputs responsive to the reference clock, and generating from the value an output corresponding to a number of partial LO cycles during the reference clock cycle;

downconverting an incoming radio frequency (RF) signal to a second frequency signal using the LO signal, wherein the downconverting causes the phase noise to be transferred to the second frequency signal; and

removing the phase noise from the second frequency signal using the digitized phase noise value.

10. The method of claim 9, further comprising downconverting the second frequency signal to a baseband signal and demodulating the baseband signal to extract message information from the baseband signal.

11. The method of claim 10, further comprising removing quantization noise from the digitized phase noise value.

12. The method of claim 11, further comprising downconverting the RF signal to the second frequency signal in a first mixer and removing the phase noise from the second frequency signal and downconverting the second frequency signal to the baseband signal in a second mixer.

13. The method of claim 12, further comprising converting the digitized phase noise value to an analog value and providing the analog value to the second mixer for mixing with the second frequency signal.

14. The method of claim 9, further comprising digitizing the phase noise value in a phase-to-digital converter (PDC) having a beat frequency corresponding to a difference between a frequency of the LO signal and a product of the reference clock and a predetermined integer value less than the beat frequency, such that the PDC does not corrupt low frequency content.

15. An apparatus comprising:

a digitally controlled oscillator (DCO) to generate a local oscillator (LO) signal;

phase digitization means coupled to the DCO for receiving a LO signal and determining a phase noise present in the LO signal, wherein the phase digitization means comprises a counter to receive the LO signal, the counter controlled by a reference clock and to generate a first portion of a digital word corresponding to a count of LO signal cycles during a cycle of the reference clock, a delay line coupled to receive the LO signal, the delay line having L stages each to provide an output, and a decoder coupled to the delay line to receive the L outputs responsive to the reference clock and generate a second portion of the digital word corresponding to a number of partial LO cycles during the reference clock cycle;

a front end mixer to receive a radio frequency (RF) signal and downconvert the RF signal to an intermediate frequency (IF) using the LO signal, wherein the phase noise is transferred to the IF signal; and

a downstream mixer coupled to the front end mixer to receive the IF signal, a second LO signal and the determined phase noise and to downconvert the IF signal including the phase noise to a baseband signal without the phase noise.

16. The apparatus of claim 15, further comprising a feed forward loop coupled between the front end mixer and the downstream mixer, the feed forward loop including the phase digitization means.

17. The apparatus of claim 16, wherein the feed forward loop further comprises a low pass filter coupled to an output of the phase digitization means to remove quantization noise generated by the phase digitization means.

18. The apparatus of claim 15, wherein a beat frequency (f₀) of the phase digitization means corresponds to a difference between a frequency of the LO signal and a product of the reference clock and a predetermined integer value less than the beat frequency, such that the phase digitization means does not corrupt low frequency content.

19. A system comprising:

a tuner to receive a radio frequency (RF) signal from a signal source and downconvert the RF signal to a baseband frequency to extract a signal channel from the RF signal, the tuner including a phase-to-digital converter (PDC) to receive a local oscillator (LO) signal used in the downconversion and to determine a digital phase noise value corresponding to a measure of phase noise present in the LO signal, and a downstream mixer to receive a first downconverted signal and remove phase noise therefrom using the digital phase noise value, wherein the PDC comprises a counter to receive the LO signal, the counter controlled by a reference clock, wherein the counter is to generate a count of LO signal cycles during a cycle of the reference clock, a first storage coupled to the counter to store the count, a delay line coupled to receive the LO signal, the delay line having L stages each to provide an output, a second storage coupled to receive the L outputs and to provide a value of the L outputs responsive to the reference clock, and a decoder coupled to the second storage to receive the values and generate a decoder output corresponding to a number of partial LO cycles during the reference clock cycle;

a demodulator coupled to the tuner to demodulate the signal channel and to generate a transport stream therefrom; and

a processor coupled to the demodulator to receive the transport stream and to process the transport stream to obtain audio visual data.

20. The system of claim 19, further comprising a feed forward loop coupled between an upstream mixer that receives the RF signal and the downstream mixer, the feed forward loop including the PDC.

21. The system of claim 20, wherein the feed forward loop further comprises a low pass filter coupled to an output of the PDC to remove quantization noise generated by the PDC.

22. The system of claim 19, wherein the digital phase noise value is provided to the demodulator for use in demodulation of the signal channel.