Memory-daughter-card-testing method and apparatus
First Claim
1. An apparatus comprising:
- a first memory card that includes;
a plurality of memory chips;
a high-speed external card interface connected to write and read data to and from the memory chips; and
a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card.
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Accused Products
Abstract
A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card'"'"'s functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card'"'"'s functions.
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Citations
21 Claims
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1. An apparatus comprising:
a first memory card that includes; a plurality of memory chips; a high-speed external card interface connected to write and read data to and from the memory chips; and a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card. - View Dependent Claims (4, 6, 7)
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2. An apparatus comprising:
a first memory card that includes; a plurality of memory chips; a high-speed external card interface connected to write and read data to and from the memory chips; a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card; and a plurality of memory controllers, each one of the plurality of memory controllers connected to control a subset of the plurality of the memory chips on the first memory card. - View Dependent Claims (3)
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5. An apparatus comprising:
a first memory card that includes; a plurality of memory chips; a high-speed external card interface connected to write and read data to and from the memory chips; a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card; and a test system operably coupled to the first memory card and configured to cause the test engine in the first memory card to test a second memory card, the test system comprising; a test fixture having a first interface connectable to the first memory card and a second interface connectable to the second memory card, such that at least some inputs from the first interface are connected to corresponding outputs of the second interface, and at least some outputs from the first interface are connected to corresponding inputs of the second interface; and a test controller operable to send configuration data through the first interface and into the first memory card to cause a testing function to be performed under the control of the first memory card when suitable first and second memory cards are connected to the test fixture.
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8. A method comprising:
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providing a first memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the first memory card writes and reads data to and from the plurality of memory chips of the first memory card; providing a second memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the second memory card writes and reads data to and from the plurality of memory chips of the second memory card, and wherein the second memory card is substantially identical to the first memory card; connecting the high-speed external card interface of the first memory card to the high-speed external card interface of the substantially identical second memory card; and testing the second memory card by writing and reading data through the high-speed interface of the first memory card and the high-speed interface of the second memory card to and from the plurality of memory chips on the second memory card under control of the first memory card. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a first memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the first memory card writes and reads data to and from the plurality of memory chips of the first memory card; a second memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the second memory card writes and reads data to and from the plurality of memory chips of the second memory card, and wherein the second memory card is substantially identical to the first memory card; means for connecting the high-speed external card interface of the first memory card to the high-speed external card interface of the substantially identical second memory card; and means for testing the second memory card by writing and reading data through the high-speed interface of the first memory card and the high-speed interface of the second memory card to and from the plurality of memory chips on the second memory card under control of the first memory card. - View Dependent Claims (16, 17, 18, 19, 20)
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21. An apparatus comprising:
a first memory card that includes; a plurality of memory chips; a high-speed external card interface connected to write and read data to and from the memory chips; a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card; and a plurality of caches operatively coupled to the plurality of memory chips on the first memory card.
Specification