Bus systems and reconfiguration methods

• US 8,127,061 B2
• Filed: 02/18/2003
• Issued: 02/28/2012
• Est. Priority Date: 02/18/2002
• Status: Active Grant

• Current Assignee: Maren Krass, Thomas Richter
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Baumgarte, Volker, Ehlers, Gerd
• Primary Examiner(s): Cleary, Thomas J
• Application Number:
  US10/504,684
• Publication Number:
  US 20070150637A1
• Time in Patent Office: 3,297 Days
• Field of Search: 710/100, 710105-108, 710/110, 710316-317, 710/200, 712 10- 12, 712/15, 716/116, 716/117
• US Class Current: 710/108
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A processor chip includes data processing elements that each has dedicated to it a respective switch for dynamically establishing an interconnection between the data processing elements conditional upon verification of a validity of the interconnection, which verification is automatically performed by at least one of the data processing elements to be interconnected.

Claims

1. A processor chip, comprising:

a bus structure; and

a multidimensional field of cells;

wherein;

for each of at least some of the cells, a respective switch is dedicated to the respective cell for dynamically establishing an interconnection over the bus structure and between the respective cell and another of the cells, data being transferable from a transmitting one of the interconnected cells to a receiving one of the interconnected cells via the interconnection;

the processor chip is adapted for at least one of the transmitting and receiving cells to automatically verify a validity of the interconnection; and

the interconnection is established conditional upon the verification of the validity.

2. The processor chip of claim 1, wherein the interconnection is established conditional upon approval of the interconnection by both of the transmitting and receiving cells.

3. The processor chip of claim 1, wherein the cells are coarsely granular logic cell units.

4. The processor chip of claim 3, wherein each of at least one of the coarsely granular logic cell units includes an arithmetic logic unit.

5. The processor chip of claim 1, wherein the verification of the validity of the interconnection depends on an availability of resources required for the interconnection.

6. The processor chip of claim 5, wherein the resources on whose availability the validity of the interconnection depends includes at least two of the transmitting cell, the receiving cell, and a bus segment of the bus structure.

7. The processor chip of claim 6, wherein the validity of the interconnection is analyzed based on identifiers assigned to at least one of the transmitting cell, the receiving cell, and the bus segment.

8. The processor chip of claim 7, wherein the validity of the interconnection is further analyzed based on an identifier assigned to a currently processed application.

9. The processor chip of claim 6, wherein the cells are coarsely granular logic cell units.

10. The processor chip of claim 9, wherein each of at least one of the coarsely granular logic cell units includes an arithmetic logic unit.

11. The processor chip of claim 5, wherein the cells are coarsely granular logic cell units.

12. The processor chip of claim 11, wherein each of at least one of the coarsely granular logic cell units includes an arithmetic logic unit.

13. The processor chip of claim 1, wherein each of the transmitting and receiving cells stores therein an identification of a configuration to which the respective cell is assigned, and the verification of the validity is performed by comparing the identifications.

14. The processor chip of claim 1, wherein the bus structure includes:

a plurality of bus segments;

two switches at an interface between two adjacent ones of the plurality of bus segments;

a first one of the switches is controllable by a first one of the two adjacent ones of the plurality of bus segments; and

a second one of the switches is controllable by a second one of the two adjacent ones of the plurality of bus segments.

15. The processor chip of claim 1, wherein the cells are reconfigurable data processing elements.

16. The processor chip of claim 1, wherein the verification includes verifying whether there is a relationship between the transmitting and receiving cells rendering them suitable for connection to each other.

17. The processor chip of claim 16, wherein the verification is performed in response to a configuration of the interconnection.

18. The processor chip of claim 1, wherein the cells include at least one of data processing elements and memory elements.