Memory hub and access method having internal prefetch buffers

• US 8,127,081 B2
• Filed: 08/04/2008
• Issued: 02/28/2012
• Est. Priority Date: 06/20/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Lee, Terry R., Jeddeloh, Joseph
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/185,615
• Publication Number:
  US 20090187714A1
• Time in Patent Office: 1,303 Days
• Field of Search: 711/137, 711/118, 711/154, 711/213, 711/145, 711/112, 711/113, 711/114, 710/22, 710/3, 710/100, 709/229, 709/250, 709/233, 709/104
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6024 History based prefetching
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Claims

1. A system for prefetching data, comprising:

a link interface configured to receive a memory request;

a memory device interface operable to transmit memory requests and to receive read data responsive to at least some of the transmitted memory requests;

a storage device configured to store data; and

a prefetch circuit coupled to the link interface, the memory device interface and the storage device, the prefetch circuit being configured to receive memory requests from the link interface and to receive at least some of the read data received by the memory device interface, the prefetch circuit operable to;

detect a pattern from which addresses to the memory requests that are likely to be accessed are predicted based on the memory requests previously received by the link interface,

based on the pattern, generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests,

couple read memory requests to the memory device interface according to the prefetch suggestions, and

cause at least some of the read data received by the memory device interface to be stored in the storage device,

wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the storage device, the data read control circuit operable to determine from read memory requests received by the link interface if the data corresponding to the read memory requests are stored in the storage device, the data read control circuit further operable to transfer the data corresponding to the read memory requests from the storage device if the data corresponding to the read memory requests are stored in the storage device,

wherein the prefetch circuit is operable to transfer the read memory requests received by the link interface to the memory device interface if the data corresponding to the read memory requests are not stored in the storage device.

2. The system of claim 1 wherein the storage device comprises a prefetch buffer configured to provide the read data stored in the storage device to the link interface responsive to subsequent memory requests received by the link interface.

3. The system of claim 1 wherein the storage device comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

4. The system of claim 1 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the storage device, the tag logic unit operable to store addresses of the data stored in the storage device, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored data, and generate a hit control signal indicative of whether an address match was determined.

5. The system of claim 4 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the storage device, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the storage device to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

6. A processor-based system, comprising:

a processor;

an input device coupled to the processor;

an output device coupled to the processor;

a storage device coupled to the processor;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a system for prefetching data, comprising;

a storage device configured to store data; and

a prefetch circuit coupled to the processor, the storage device, and the plurality of memory devices, the prefetch circuit being configured to;

receive memory requests from the processor,

receive at least some of the read data received from the plurality of memory devices,

detect a pattern from which addresses to the memory requests that are likely to be accessed are predicted based on the memory requests previously received from the processor,

based on the pattern, generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests,

couple read memory requests to the memory devices according to the prefetch suggestions, and

cause at least some of the read data received from the plurality of memory devices to be stored in the storage device,

wherein the prefetch circuit further comprises a data read control circuit coupled to the plurality of memory devices, processor, and the storage device, the data read control circuit operable to determine from read memory requests received from the processor if the data corresponding to the read memory requests are stored in the storage device, the data read control circuit further operable to transfer the data corresponding to the read memory requests from the storage device to the processor if the data corresponding to the read memory requests are stored in the storage device, the prefetch circuit further being operable to transfer the read memory requests received from the processor to the plurality of memory device if the data corresponding to the read memory requests are not stored in the storage device.

7. The system of claim 6 wherein the storage device comprises a prefetch buffer configured to provide the read data stored in the storage device to the processor responsive to subsequent memory requests received from the processor.

8. The system of claim 6 wherein the storage device comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

9. The system of claim 6 wherein the data read control circuit comprises a tag logic unit coupled to the processor and the storage device, the tag logic unit operable to store addresses of the data stored in the storage device, the tag logic unit further operable to receive memory requests from the processor, compare the addresses of the received memory requests to the addresses of the stored data, and generate a hit control signal indicative of whether an address match was determined.

10. The system of claim 9 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the storage device, to the tag logic unit and to the plurality of memory devices, the multiplexer operable to transfer the data input from the storage device to the processor responsive to an active hit control signal received from the tag logic unit, and to transfer data input from the plurality of memory devices to the processor responsive to an inactive hit control signal received from the tag logic unit.

11. A method of prefetching data in a memory system having a memory module containing a plurality of memory devices, the method comprising:

receiving memory requests at the memory module for access to memory cells in the plurality of memory devices;

coupling the received memory requests to the memory devices within the memory module, at least some of the memory requests being memory requests to read data;

receiving read data within the memory module responsive to the read memory requests;

prefetching data from the memory devices that are likely to be accessed using predicted addresses based on the received memory requests and storing the prefetched data;

dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride;

storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the respective stride;

transferring the prefetched data from the memory module responsive to subsequent memory requests;

storing in the memory module prefetch addresses corresponding to the stored prefetched data;

receiving memory request addresses at the memory module corresponding to subsequent memory requests;

comparing each received memory request address to the prefetch addresses within the memory module;

determining that the requested read data are stored in the memory module as prefetched data in the event of an address match;

transferring read data stored as prefetched data from the memory module responsive to determining that the requested read data are stored as prefetched data in the memory module; and

transferring read data from the memory devices responsive to determining that the requested read data are not stored as prefetched data, the read data being transferred from the memory module.

12. The method of claim 11, further comprising prefetching data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

13. The method of claim 11 wherein prefetching data from the memory devices comprises prefetching data only when the memory requests are not being received.

14. The method of claim 11 further comprising selectively enabling prefetching based on the nature of the received memory requests.

15. The method of claim 11 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals at the memory module corresponding to the memory requests.

16. A method of prefetching data within a memory module, comprising:

receiving memory requests at the memory module;

coupling the received memory requests to the memory devices within the memory module, at least some of the memory requests being memory requests to read data;

receiving read data responsive to the read memory requests;

prefetching data from the memory devices within the module that are likely to be accessed using predicted addresses devices based on the received memory requests;

storing the prefetched data within the memory module;

dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride;

storing the prefetched data indicative of the predicted addresses in the section corresponding to the respective stride;

transferring the prefetched data stored in the memory module from the memory module responsive to subsequent memory requests;

storing prefetch addresses corresponding to the stored prefetched data within the memory module;

receiving memory request addresses at the memory module corresponding to subsequent memory requests;

comparing each received memory request address to the prefetch addresses within the memory module;

in the event of an address match, determining within the memory module that the requested read data are stored as prefetched data within the memory module;

transferring from the memory module read data stored as prefetched data within the memory module responsive to determining that the requested read data are stored within the memory module as prefetched data; and

transferring read data from the memory devices responsive to determining that the requested read data are not stored within the memory module as prefetched data.

17. The method of claim 16 further comprising prefetching data from memory cells in the memory devices that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

18. The method of claim 16 wherein prefetching data from the memory devices comprises prefetching data only when the memory requests are not being received by the memory module.

19. The method of claim 16 further comprising selectively enabling prefetching based on the nature of the memory requests received by the memory module.

20. The method of claim 16 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals at the memory module corresponding to the memory requests.