Apparatus for executing programs for a first computer architechture on a computer of a second architechture

• US 8,127,121 B2
• Filed: 09/25/2007
• Issued: 02/28/2012
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Van Dyke, Korbin S., Yates, Jr., John S., Storch, Matthew F., Nijhawan, Sandeep, Jurich, Dale R.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US11/904,007
• Publication Number:
  US 20080216073A1
• Time in Patent Office: 1,617 Days
• Field of Search: None
• US Class Current: 712/244
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS

Abstract

Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread'"'"'s context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.

Claims

1. A computer, comprising:

an entry handler block configured to;

process an entry exception raised on entry to a pre-existing operating system at a specified entry point or on a specified condition without modifying the pre-existing operating system of the computer;

save a context of an interrupted thread to a memory;

modify the thread context; and

deliver the modified thread context to the operating system;

an exit handler block configured to;

process a resumption exception raised on resumption from the operating system when such resumption is complementary to one of the specified entry exceptions without modifying the operating system; and

restore the context saved by a corresponding execution of the entry handler from the memory;

a thread scheduler block configured to;

schedule concurrent threads of control, each thread having an associated context; and

maintain an association between a thread and a set of computer resources of the associated context;

wherein an association between one of the threads and an extended context of the thread is maintained through a context change induced by the thread scheduler block or by the operating system, without modifying the thread scheduler block or the operating system, the extended context including resources of the computer beyond those resources associated with the thread;

a first detector block configured to;

detect a specified entry to the operating system from an interrupted thread of the computer; and

raise the entry exception; and

a second detector block configured to;

detect a complementary resumption exception;

raise the resumption exception; and

return control to the interrupted thread.

2. The computer of claim 1, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer.

3. The computer of claim 1, wherein the operating-system-maintained resources of the thread context include data registers of the non-native computer architecture, the computer further comprising:

a modifier block configured to modify at least half of the data registers of the portion of the thread context maintained by the operating system before delivering the thread to the non-native operating system.

4. The computer of claim 1, wherein:

the operating system and the thread execute in different instruction sets of the computer; and

the entry and exit exceptions are automatically generated on a transition between the thread instruction set and the operating system instruction set.

5. The computer of claim 2, which additionally executes an operating system native to the computer, the computer further comprising:

a classifier block configured to determine the operating system for handling each interrupt or exception.

6. The computer of claim 1, wherein the operating system and the interrupted thread execute in different instruction set architectures of the computer.

7. The computer of claim 3, wherein the

modifier block is further configured to redundantly write data to at least some of the modified registers to enable checking of the validity of the contents of the context in the exit handler block.

8. The computer of claim 1, wherein the memory is further configured to:

save a portion of the context of the computer during servicing the entry exception;

alter the context of an interrupted thread; and

deliver the interrupted thread and its corresponding context to the operating system.

9. The computer of claim 1, wherein the entry handler block is further configured to modify the thread context to include a linkage return address for resumption of the thread.

10. The computer of claim 9, wherein the modification leaves at least half of the bits of the linkage return address intact.

11. The computer of claim 4, further comprising:

a register set to a value that specifies actions to be taken by the entry handler block or the exit handler block, invoked on the transition between instruction sets, to convert operands from one form to another to conform to a data storage convention of the destination instruction set.

12. The computer of claim 3, wherein at least some of the modified registers are overwritten by a timestamp.

13. The computer of claim 3, wherein at least some of the modified registers are overwritten by information indicating a memory location at which at least the portion of the thread context to be modified is saved.

14. The computer of claim 1, further comprising:

a delay block configured to delay deferring delivery of an interrupt before interrupting the thread by a time sufficient to allow the thread to reach a checkpoint, wherein the checkpoint is a point in the execution of the thread where the amount of extended context is reduced.

15. The computer of claim 1, further comprising:

a service block configured to receive a linkage return address at which to resume execution on completion of the service, the linkage return address deliberately chosen so that an attempt to execute an instruction from the linkage return address on return from the service block raises a program execution exception;

a processor attempting to execute the instruction at the linkage return address and raising the program execution exception, on return from the service block; and

a controller returning control to a caller of the service block, after servicing the program execution exception.

16. The computer of claim 15, wherein the linkage return address points to a memory page having a memory attribute that raises the program execution exception on at attempt to execute an instruction from the memory page.

17. The computer of claim 1, wherein the memory for storing the thread context is selected from a pool of storage locations managed by a queuing discipline, in which empty storage locations are allocated from the head of a queue, recently-emptied storage locations for reuse are enqueued at the head of the queue, and full storage locations to be caved are queued at the tail of the queue.

18. The computer of claim 1, further comprising:

a controller configured to roll execution of the thread back to a checkpoint, wherein the checkpoint is a point in the execution of the thread where the amount of extended context is reduced.