Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode

• US 8,127,152 B2
• Filed: 11/19/2004
• Issued: 02/28/2012
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Bystrom, Todd W., May, Bradley A., Davis, Paul G.
• Primary Examiner(s): Kim, Hong
• Application Number:
  US10/993,046
• Publication Number:
  US 20050120161A1
• Time in Patent Office: 2,657 Days
• Field of Search: 711/170, 711/167, 711/105, 711/154, 713/400, 713/500, 713/401, 713/300, 713/320, 365/233, 365/194, 365/233.1, 365/226
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Claims

1. A method of operation of an integrated circuit memory device having an array of memory cells, the method comprising:

during an initialization sequence, conducting initialization operations of the integrated circuit memory device at a first frequency of operation;

during the initialization sequence, storing a value representative of a period of time to elapse between exiting from a power down mode and a time at which the integrated circuit memory device is capable of receiving a command, wherein the command specifies one of a memory access operations; and

performing memory access operations of the integrated circuit memory device at a second frequency of operation, wherein the second frequency is higher than the first frequency, wherein the memory access operations include a read operation and a write operation.

2. The method of claim 1, wherein the second frequency is higher than the first frequency by at least several hundred megahertz.

3. The method of claim 2, wherein the second frequency is approximately equal to four hundred megahertz and the first frequency is approximately equal to one megahertz.

4. The method of claim 2, wherein the second frequency is approximately equal to fifty megahertz and the first frequency is approximately equal to one megahertz.

5. The method of claim 1, further including transitioning operation of the integrated circuit memory device from the first frequency of operation to the second frequency of operation.

6. The method of claim 1, further including receiving the command, wherein the command specifies the write operation, wherein the integrated circuit memory device inputs data to be written to the array of memory cells during the write operation.

7. The method of claim 1, further including receiving the command, wherein the command specifies the read operation, wherein the integrated circuit memory device outputs read data accessed from the array of memory cells during the read operation.

8. The method of claim 7, further including:

synchronizing the output of the read data with a clock signal using a delay lock loop circuit; and

outputting the read data using the clock signal, wherein the clock signal oscillates at the second frequency of operation.

9. The method of claim 1, further including:

receiving a first clock signal, wherein the first clock frequency oscillates at the first frequency of operation; and

receiving a second clock signal, wherein the second clock frequency oscillates at the second frequency of operation.

10. The method of claim 1, further including:

during the initialization sequence;

receiving power;

after receiving power, starting a clock signal; and

receiving an initialization command, after an amount of time has elapsed from starting the clock signal.

11. The method of claim 1, further including, during the initialization sequence, programming a plurality of registers on the integrated circuit memory device, the plurality of registers to store a plurality of values that configure operation of the integrated circuit memory device in accordance with a plurality of timing parameters.

12. The method of claim 11, wherein the plurality of timing parameters includes:

a time to access a row of the integrated circuit memory device;

a time between a row access of the integrated circuit memory device and a column access of the integrated circuit memory device;

a time between a row access of the integrated circuit memory device and a precharge operation of the integrated circuit memory device;

a time between a row sense applied to a first bank of the integrated circuit memory device and a row sense applied to a second bank of the integrated circuit memory device; and

a time between a precharge operation applied to a first bank of the integrated circuit memory device and a precharge operation applied to a second bank of the integrated circuit memory device.

13. The method of claim 11, wherein each value of the plurality of values represents a number of clock cycles of a clock signal for each timing parameter of the plurality of timing parameters.

14. The method of claim 13, wherein each value is selected by dividing a time period of each timing parameter by the period of the clock signal to select the value in terms of the number of clock cycles of the clock signal.

15. The integrated circuit memory device of claim 1, wherein the memory access operations are performed during the initialization sequence.

16. The method of claim 1, further comprising storing a value that represents a number of clock cycles between receiving a read request and outputting data, wherein the value is selected to levelize a read domain of the integrated circuit memory device with a read domain of other integrated circuit memory devices in a system, wherein storing the value is performed during the initialization sequence.

17. A method of controlling an integrated circuit memory device, the method comprising:

providing to the integrated circuit memory device during an initialization sequence, commands to conduct initialization operations at a first frequency of operation;

during the initialization sequence, providing a value to the integrated circuit memory device, wherein the value is representative of a period of time to elapse between exiting from a power down mode and a time at which the integrated circuit memory device is capable of receiving a command that specifies a memory access operation; and

providing the command to the integrated circuit memory device that specifies the memory access operation, wherein the memory access operation is conducted at a second frequency of operation, wherein the second frequency is higher than the first frequency.

18. The method of claim 17, wherein the command that specifies the memory access operation specifies a read operation, wherein the integrated circuit memory device outputs data accessed from the array of memory cells during the read operation.

19. The method of claim 17, further including, during the initialization sequence, providing, to the integrated circuit memory device, a value that is representative of a number of clock cycles of a clock signal to separate a row command and a column command.

20. The method of claim 17, wherein providing the command that specifies the memory access operation is provided during the initialization sequence.

21. The method of claim 17, further including, during the initialization sequence, determining a value that is representative of a number of clock cycles of a clock signal to separate receipt of a read command by the integrated circuit memory device and data output in response to the read command by the integrated circuit memory device, wherein determining the value is conducted to levelize a read response time of the integrated circuit memory device with a read response time of other integrated circuit memory devices in a system.

22. The method of claim 17, further including, during the initialization sequence, providing an initialization command to the integrated circuit memory device after an amount of time has elapsed between a clock signal being started and a time at which the integrated circuit memory device is ready to receive the initialization command.

23. The method of claim 17, further including, during the initialization sequence, programming a plurality of registers on the integrated circuit memory device, the plurality of registers to store a plurality of values that configure operation of the integrated circuit memory device in accordance with a plurality of timing parameters.

24. The method of claim 17, further including generating a plurality of values to configure operation of the integrated circuit memory device in accordance with a plurality of timing parameters, wherein the plurality of timing parameters includes:

a time to access a row of the integrated circuit memory device;

a time between a row access of the integrated circuit memory device and a column access of the integrated circuit memory device;

a time between a row access of the integrated circuit memory device and a precharge operation of the integrated circuit memory device;

a time between a row sense applied to a first bank of the integrated circuit memory device and a row sense applied to a second bank of the integrated circuit memory device; and

a time between a precharge operation applied to a first bank of the integrated circuit memory device and a precharge operation applied to a second bank of the integrated circuit memory device.

25. The method of claim 24, wherein each value of the plurality of values represents a number of clock cycles of the clock signal for each timing parameter of the plurality of timing parameters.