Error correction code generation method and memory control device
First Claim
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1. An error correction code generation method, comprising:
- storing data of a cache line on which a store data accompany with a store instruction is to be written to a register prior to writing the store data in a cache memory;
detecting an error of the data of the cache line to be written in the cache memory;
writing the store data that is confirmed to have no errors in the cache memory;
merging the data stored in the register with the store data in the cache memory accompany with the store instruction; and
generating an error correction code for a result of the merging.
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Abstract
A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
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Citations
8 Claims
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1. An error correction code generation method, comprising:
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storing data of a cache line on which a store data accompany with a store instruction is to be written to a register prior to writing the store data in a cache memory; detecting an error of the data of the cache line to be written in the cache memory; writing the store data that is confirmed to have no errors in the cache memory; merging the data stored in the register with the store data in the cache memory accompany with the store instruction; and generating an error correction code for a result of the merging. - View Dependent Claims (2, 3, 4)
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5. A cache memory control device, comprising:
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a buffer that stores data in accordance with a store instruction; a register that stores data of a cache line on which a data is to be written in accordance with store instruction, prior to writing the store data in a cache memory; a detection unit that detects an error of the data of the cache line to be written in the cache memory; a merge circuit that merges the data stored in the register with the data stored in the cache memory accompany with the store instruction; and an error correction code generation circuit that generates an error correction code for a result of the merger, wherein the store data which is confirmed to have no errors is written in the cache memory. - View Dependent Claims (6, 7, 8)
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Specification