Methods of manufacturing power semiconductor devices with shield and gate contacts

• US 8,129,245 B2
• Filed: 08/26/2011
• Issued: 03/06/2012
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Stokes, Richard, Yedinak, Joseph A., Kraft, Nathan L., Kocon, Christopher B.
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Naraghi, Ali
• Application Number:
  US13/219,281
• Publication Number:
  US 20110312166A1
• Time in Patent Office: 193 Days
• Field of Search: 438/151, 438154-157, 438/173, 438175-176, 438137-138, 438218-219, 438268-270, 438259-260, 257/E27.009, 257/E29.201
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate;

forming a dielectric layer over the epitaxial layer and patterning the dielectric layer;

etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer;

forming a first oxide layer across a top surface of the substrate including the active trench;

forming a first conductive layer on top of the first oxide layer;

etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer;

forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first edge region outside of the active trench;

forming a third oxide layer over the second conductive layer;

etching a first opening through the third oxide layer to expose the second conductive layer outside of the active trench;

etching a second opening through the second oxide layer outside of the active trench to expose the first conductive layer but not the second conductive layer;

the first opening and the second opening located in the first edge region and filling the first opening and the second opening with a conductive material.

2. The method of claim 1 further comprising forming plurality of active trenches in the longitudinal direction and forming a perimeter trench with a plurality of extensions in the longitudinal direction that are staggered with respect to the active trenches so that there is an offset between the plurality of extensions of the perimeter trench and the active trenches.

3. The method of claim 1 further comprising forming plurality of active trenches in the longitudinal direction and forming a perimeter trench with a plurality of extensions in the longitudinal direction that are staggered with respect to the active trenches so that there is no offset between the plurality of extensions of the perimeter trench and the active trenches.

4. The method of claim 1 further comprising forming a third conductive layer over the third oxide layer and contacting the conductive material in the first opening and the second opening to electrically connect the first conductive layer and the second conductive layer.

5. The method of claim 1 further comprising electrically connecting the first opening to a first metal contact and the second opening to a second metal contact.

6. The method of claim 1 wherein the step of depositing a dielectric layer further comprises depositing a layer of silicon dioxide.

7. The method of claim 1 wherein the first conductive layer, the second conductive layer are polysilicon.

8. The method of claim 1 wherein

the first conductive layer is directly formed over the first oxide layer;

the second oxide layer is directly formed over the first conductive layer;

the second conductive layer is directly formed over the second oxide layer; and

the third oxide layer is directly formed over the second conductive layer.

9. The method of claim 1 wherein the first conductive layer and the second conductive layer are formed with substantially the same thickness.

10. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate;

forming a dielectric layer over the epitaxial layer and patterning the dielectric layer;

etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer;

forming a first oxide layer across a top surface of the substrate including the active trench;

forming a first conductive layer on top of the first oxide layer;

etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer;

forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first edge region outside of the active trench;

forming a third oxide layer over the second conductive layer;

etching a first opening through the third oxide layer to expose the second conductive layer in the first edge region outside of the active trench;

etching a second opening through the second oxide layer outside of the active trench in the first edge region to expose the first conductive layer but not the second conductive layer; and

filling the first opening and the second opening with a conductive material.

11. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate;

forming a dielectric layer over the epitaxial layer and patterning the dielectric layer;

etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer;

forming a first oxide layer across a top surface of the substrate including the active trench;

forming a first conductive layer on top of the first oxide layer;

etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer;

forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench;

forming a third oxide layer over the second conductive layer;

etching a first opening through the third oxide layer to expose the second conductive layer in the first region outside of the active trench;

etching a second opening through the second oxide layer outside of the active trench to expose the first conductive layer but not the second conductive layer, the first opening and the second opening on a same side of the active trench; and

filling the first opening and the second opening with a conductive material.